Wb2axip Alternatives

Similar projects and alternatives to wb2axip

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NOTE: The number of mentions on this list indicates mentions on common posts. Hence, a higher number means a better wb2axip alternative or higher similarity.

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Posts

Posts where wb2axip has been mentioned. We have used some of these posts to build our list of alternatives and similar projects - the last one was on 2021-07-22.
  • SoC FPGA design to ASIC
    reddit.com/r/FPGA | 2021-07-22
    How about an interconnect? I've posted just about all the necessary components for building one. If you look hard enough, you'll find that others have done so as well.
  • FPGA development automation practices
    reddit.com/r/FPGA | 2021-07-21
    Formal verification checks. Before checking anything into a repository, it's important to know that any changes that have been made to it haven't broken the formal proof of it. Therefore, I keep make files in my bench/formal directories. These makefiles (example) key off of the production of one (or many) proofname/PASS file. If the file is out of date or doesn't exist, the proof needs to be re-run before updating any repository. Here's an example make dependency for my
  • AXI4 read and write latencies
    reddit.com/r/FPGA | 2021-07-11
    Beware of going through Xilinx's AXI4 to AXI4-lite bridge. A minimum bridge cost is another 2 cycles of latency. (See for example slide 24 of this brief.) However, Xilinx's bridge has an area optimized mode that only allows a single packet, either read or write but not both, on the AXI4-lite side of their bridge at any given time. You might find this bridge gets better throughput--as illustrated in the slide referenced above, but you can't get around the minimum bridge cost.
    reddit.com/r/FPGA | 2021-07-11
    I've been doing several experiments to see if I can measure AXI4 latency and throughput. The measurement IP I'm using is posted here. It's got an AXI4-lite slave control port, together with an AXI4 full monitor port. Once you write a "start" signal to the AXI4-lite slave port, the core starts calculating statistics regarding the AXI4 full port. The statistics themselves are described in the documentation at the top of the file. From these, the core is designed to be able to measure both read and write latencies.
  • Vivado 2021.1 is out, but does it work? Have they fixed their IP yet?
    reddit.com/r/FPGA | 2021-06-24
    If you need to start with a custom design, then start with this one. It's a really easy design to work with--so much so that almost all of my new AXI-lite designs are starting from this template. Examples: 1, 2, 3, etc.
    reddit.com/r/FPGA | 2021-06-24
    Their AXI S2MM DMA design has some annoying quirks to it. You can either learn to work around them, or you can use an open source S2MM module that doesn't have these problems. What are the quirks? A) It will accept data and then lock up if the data ever shows up before the design has been configured, B) It will always stop on TLAST--even if you want the transfer to keep going, and C) It will lock up again if you don't provide a TLAST signal at the end of the packet. At least those are the quirks I remember off the top of my head. Xilinx's official position is that these aren't "bugs", but rather "features" of their design.
  • Programming RISC-V Processor: Educational Project, Looking for A Group
    reddit.com/r/FPGA | 2021-05-16
    What bus will you be using? I can provide an AXI interconnect, and AXI DMAs..
  • What modules/hardware would you like to see?
    reddit.com/r/FPGA | 2021-05-14
    I've posted quite a few AXI designs on github. These include an AXI Crossbar, an AX DMA, and even an AXI scatter-gather based DMA. Some of my recent postings even include instruction or [data](instruction caches.
    reddit.com/r/FPGA | 2021-05-14
    The next key to understanding AXI4 (same as AXI-full) is to understand how AXI addressing works. What are FIXED, INCR, and WRAP addressing modes, and how do they work? Xilinx's demo only ever handled INCR and WRAP addressing as I recall, and then only did it right if the beat size matched the bus size. You can find a more complete discussion on AXI addressing here. The component built in that blog article has since been optimized some more, but I still use it in all of my AXI4 (full) slave designs--it just makes handling addressing easy. You can find a recent copy of my optimized version here.
  • Zynq PS to PL Latency
    reddit.com/r/FPGA | 2021-05-13
    I'm not sure the best way to measure latency from PS load/store instruction to PL AWVALID, WVALID, or ARVALID. However, it is possible to measure latency within the PL a lot easier: measure the time from ARVALID to RVALID (for example), or AWVALID to BVALID or WVALID && WLAST to BVALID. You'll need to make your measurements between the ARM and the interconnect.
  • Microblaze Project Ideas?
    reddit.com/r/FPGA | 2021-05-04
    Like I said above, neither the MIG DDRx controllers nor Xilinx's AXI block RAM controller support exclusive access transactions--making multitasking on a Microblaze a difficult or even impossible task. On the other hand, there is an open source block RAM controller that does support exclusive access transactions over AXI.
  • Shout-out to this blog post that actually explains what the hell AXI DMA does
    reddit.com/r/FPGA | 2021-04-25
    In my own version, the list contains three words per entry: the source address, the destination address, and the length. The SG DMA engine just reads that information, uses it to program the DMA, waits for the DMA to complete, and then programs the DMA with the values from the next table entry.
  • CPU DESIGN
    reddit.com/r/FPGA | 2021-04-05
    There are also open source versions of many of the pieces you will need. I now use an open source crossbar interconnect for most of my designs. I use AutoFPGA to connect all the pieces together. I mentioned my flash controller above, but I also have a SD Card controller I've used quite successfully. I've also posted a UART to Wishbone bridge and discussed network debugging, both of which I use routinely with the ZipCPU. If for no other reason, these components allow me to load or update software on my CPU even after it's been placed into an FPGA. Of course, many of those components are tied to a Wishbone bus infrastructure. You may find you need a bridge of some type to connect different buses structures together--memory naturally tends to operate at one width and clock, video at another, and your CPU at another, so it helps at times to have a universal bus adapter kit handy.
  • Need Advice for learning digital design and ASIC and FPGA design flow
    reddit.com/r/FPGA | 2021-03-24
    Given my own personal experiences, I would not trust any design component that interacts with a bus without first formally verifying that component. I've just been burned too many times. I now have bus verification properties for Wishbone, AXI-lite, AXI, and APB that I use for this purpose, together with quite the set of formally verified bus designs. Other things I would insist on verifying before using include CPUs and hardware controllers for such things as SDRAMs or flash devices.
  • Definition of AXI, AHB, and APB Bus Hang
    reddit.com/r/FPGA | 2021-03-16
    I generally keep track of a couple of bugs when examining buses. You can see my taxonomy of four basic bus errors here. One not listed there is that a given component should only be able to hold xREADY low for a maximum (application dependent) period of time.

Stats

Basic wb2axip repo stats
24
210
8.3
about 1 month ago