Wb2axip Alternatives

wb2axip reviews and mentions

• Simple skid buffer implementation
  3 projects | /r/FPGA | 10 Jan 2023

  I've always been partial to my own skidbuffer article and implementation. (You'd expect me to be, they're my own ...) I get your point, though, about some applications needing a registered output. I've come across many, as requirements change from one project to the next. This is why, in my own implementation, I have parameters allowing me to adjust which implementation I'm using. In this case in particular, I have a parameter adjusting whether or not the output is registered. (The outgoing READY signal, though, is always registered--that's the point of the skid buffer in the first place, and what keeps it from being a regular buffer.)

• Testing Axi Slaves in Simulation
  1 project | /r/FPGA | 4 Jan 2023

  Ref: [1], [2]

• Looking to implimenting an autocorrelation function (ACF) into one of my projects.
  3 projects | /r/FPGA | 24 Nov 2022

  Have you considered this article? It goes over the basics of the autocorrelation function, while also illustrating how you can build one with a Wishbone interface. Further, the Verilator logic for this function is kept and maintained on github here. Sure, it uses Wishbone. If you want to use AXI you can either use a bridge, or rework the the interface (it's not that hard ...).

• Guys can u send me some github repositories on some simple project on system verilog with functionality like with couple functions ? Its my first reddit post in my life.
  1 project | /r/FPGA | 14 Nov 2022

  If this is what you want, though, then consider checking out the apply_wstrb function in my wb2axip repository. Perhaps the easyaxil might be the easiest one to start with.

• Reference of verification IPs
  7 projects | /r/FPGA | 2 Nov 2022

  The worst thing that can happen on a bus is a protocol error that causes the device to lock up. Sadly, such errors have been common when using AXI or AXI-Lite--especially since traditional "verification IP" bus models won't catch all circumstances. This is why I make a general (personal) rule that nothing should touch a bus unless it has been formally verified. This check basically guarantees that every bus request gets one (and only one) response. It's not sufficient to verify an IP fully, but it's a good start. You can find my formal verification models for AXI-Lite, Wishbone, and (to some extent) Avalon in this repository. I've also been known to make my full AXI model available to Patreon sponsors of my blog.

• A simple AXI-Lite register file
  1 project | /r/FPGA | 24 Oct 2022

  As an experiment, I tried a formal first approach using u/ZipCPU's faxil_slave.v.

• AXI-Lite register bank revisited
  1 project | /r/FPGA | 22 Oct 2022

  I then moved on to an internal desk check of the design ... 1. skydivertricky is right: AXI does not allow timeouts. If you implement an AXI timeout, you will risk crashing any system using your design. Your timeout implementation is therefore broken, and will risk crashing any system attempting to interact with your design. This applies to both your read and write paths. 2. Sure enough, your write state machine looks only for the write address strobe during the idle state. If write data shows up early, the write data will be forgotten causing the system to hang. This was one of the bugs caught by SymbiYosys and mentioned above. 3. Your design has a nasty sequencing bug within it: wren is set on the clock _after the transaction takes place. As a result, the s_axi_awaddr and s_axi_wdata values used within your design may contain garbage within them. Indeed, they may be already set for the next transaction, or the master may put some other value in them. As a result, writes to your design may work for some masters, or more likely will not work at all. (They won't work with any of my own open source AXI-lite masters.) 4. I would recommend implementing WSTRB. There are plenty of implementations out there that will use this value, particularly when crossing from one bus width to another, but also when the CPU attempts to write less than a full word. I've been burned more than once by acting on a write when WSTRB was zero. 5. As predicted by SymbiYosys, your read data calculation is also broken. Specifically, it depends upon the value in ARADDR on the cycle following the cycle where ARVALID && ARREADY. This breaks protocol, and is likely to give you some very unexpected results. 6. While not technically broken, I would recommend that your reads ignore the bottom two bits of address. If you do this, the reads will then work if the CPU issues a load-byte or load-halfword instruction. The same applies to the writes--you should be looking at all but the bottom two bits (for a bus with 32-bit data words, like AXI-lite).

• Xilinx FIFO generator for skid buffer?
  2 projects | /r/FPGA | 20 Oct 2022

  Can a FIFO be generated to use the AXI stream protocol? Absolutely! Check out this FIFO: - S_AXIS_VALID can be fed to the write port, i_wr - S_AXIS_READY is the compliment of the FIFO full output, o_full - S_AXIS_DATA can be fed to the incoming data port, i_data - M_AXIS_VALID is the compliment of the FIFO empty output, o_emtpy - M_AXIS_READY can be fed directly to the read port, i_rd - M_AXIS_DATA can be read directly from the outgoing data port, o_data - If you want to support other AXI Stream signals, they can simply be concatenated with the data signals above.

• Connecting custom IP to microblaze
  1 project | /r/FPGA | 24 Sep 2022

  I recently connected my own IP to a Microblaze core via the AXI-lite interface. Vivado has a tool to generate AXI IP, but it's broken so I used this implementation of an AXI-lite slave. It comes with some registers that'll be accessible in the processors address space. Here is a more detailed explanation of the linked implementation.

• Implement Synchronous FWFT FIFO in BRAM
  1 project | /r/FPGA | 7 Jul 2022

  Here's an example of an FWFT FIFO written in a vendor independent fashion. Yes, it requires a bit of wizardry to get right--primarily in how the read address is calculated, but I've used it for years now and it's held up nicely for me.

• A note from our sponsor - SaaSHub
  www.saashub.com | 24 Apr 2024

  SaaSHub helps you find the best software and product alternatives Learn more →