biriscv
32-bit Superscalar RISC-V CPU (by ultraembedded)
wbicapetwo
Wishbone to ICAPE interface conversion (by ZipCPU)
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| biriscv | wbicapetwo | |
|---|---|---|
| 6 | 2 | |
| 749 | 8 | |
| - | - | |
| 0.0 | 0.0 | |
| over 2 years ago | about 4 years ago | |
| Verilog | Verilog | |
| Apache License 2.0 | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
biriscv
Posts with mentions or reviews of biriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-21.
wbicapetwo
Posts with mentions or reviews of wbicapetwo.
We have used some of these posts to build our list of alternatives
and similar projects.
- Can an FPGA program itself?
-
Xilinx ICAP issues
Perhaps an example design using the ICAPE2 port might help?
What are some alternatives?
When comparing biriscv and wbicapetwo you can also consider the following projects:
riscv - RISC-V CPU Core (RV32IM)
openarty - An Open Source configuration of the Arty platform
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
wbuart32 - A simple, basic, formally verified UART controller
sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces
wbscope - A wishbone controlled scope for FPGA's
zipcpu - A small, light weight, RISC CPU soft core
vgasim - A Video display simulator
RISC-V - Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
wb2axip - Bus bridges and other odds and ends