edalize
rggen
Our great sponsors
edalize | rggen | |
---|---|---|
4 | 3 | |
587 | 277 | |
- | 4.3% | |
7.3 | 7.7 | |
5 days ago | 2 months ago | |
Python | Ruby | |
BSD 2-clause "Simplified" License | MIT License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
edalize
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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Compiling Code into Silicon
This reminds me very much of edalize[1], which does something very similar.
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
rggen
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RgGen update (support C header file generation)
RgGen is a code generation tool for configuration and status registers. RgGen can generate SV/Verilog/VHDL RTL, UVM RAL model and Markdown documents from readable register map specifications. https://github.com/rggen/rggen
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RgGen update
I just released the latest RgGen v0.26.0! https://github.com/rggen/rggen/releases/tag/v0.26.0
What are some alternatives?
PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
apio - :seedling: Open source ecosystem for open FPGA boards
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
PeakRDL-ipxact - Import and export IP-XACT XML register models
icestudio - :snowflake: Visual editor for open FPGA boards
sphinx-vhdl
opentitan - OpenTitan: Open source silicon root of trust
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
hdl_checker - Repurposing existing HDL tools to help writing better code