Compiling Code into Silicon

• freepdk-45nm

  0 96 10.0 Verilog

  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

  

  Pretty neat, a python tool that converts Verilog to an IC layout so that you can make your own custom SOC (assuming you have a substantial budget to pay for fab).

  Since it's not clearly stated on the front page, I had to go digging to figure out what processes it supports. Looks like FreePDK45, which is "an open-source generic process design kit (PDK) (i.e., does not correspond to any real process and cannot be fabricated)" [0], ASAP7 "Warning Work in progress (not ready for use)" [1] and Skywater130 which "As of May 2020, this repository is targeting the SKY130 process node. If the SKY130 process node release is successful then in the future more advanced technology nodes may become available." [2] The floorplanner supports their ZeroSOC [3] which I guess is based on TitanSOC [4]

  If this sounds negative, it's not, I just couldn't figure out what processes this was intended for without digging. ASAP7 is Arm and NCSU, and Skywater130 is Skywater and Google.

  [0] https://github.com/mflowgen/freepdk-45nm

• skywater-pdk

  5 2,701 0.0 Python

  Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

  

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• zerosoc

  0 48 0.0 SystemVerilog

  Demo SoC for SiliconCompiler.

  

• opentitan

  4 2,053 9.9 SystemVerilog

  OpenTitan: Open source silicon root of trust

  

• gssi

  0 3 10.0 TeX

  Stuff I worked on while at GSSI (L'Aquila, Italy)

  Personally I have fond memories of MyHDL [0], which may be seen as another "code-to-silicon" converter (or at least as the first step of a code-to-silicon workflow). I used it only briefly, and on a school project that had surprisingly little to do with actual hardware design [1], but it really felt "Pythonic" in the best possible way.

  [0]: https://www.myhdl.org/

  [1]: https://github.com/lou1306/gssi/tree/master/2pc

• myhdl

  0 966 0.0 Python

  The MyHDL development repository

  

  Personally I have fond memories of MyHDL [0], which may be seen as another "code-to-silicon" converter (or at least as the first step of a code-to-silicon workflow). I used it only briefly, and on a school project that had surprisingly little to do with actual hardware design [1], but it really felt "Pythonic" in the best possible way.

  [0]: https://www.myhdl.org/

  [1]: https://github.com/lou1306/gssi/tree/master/2pc

• Verilog.jl

  0 43 0.0 Julia

  Verilog for Julia

  

  It doesn't have to be. I once made a julia->verilog transpiler that even recompiled your julia functions with verilator, so you could verify that the code was correct.

  https://github.com/interplanetary-robot/Verilog.jl

  Of course, gaining traction on something like this is tricky.

  I actually think Erlang/BEAM would be a great choice for making EDA tools, because it has concurrent execution model that you could probably very easily make play nice in rudimentary simulations of circuits that have triggers (`always @` sort of stuff.

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• edalize

  2 556 7.8 Python

  An abstraction library for interfacing EDA tools

  This reminds me very much of edalize[1], which does something very similar.

  [1]: https://github.com/olofk/edalize

• chisel

  7 3,292 9.6 Scala

  Chisel: A Modern Hardware Design Language (by chipsalliance)

  

  Seems similar to the Chisel compiler for RISC-V:

  https://github.com/chipsalliance/chisel3

• openlane

  3 1,068 0.0 Python

  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

  

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