Python Verilator

Open-source Python projects categorized as Verilator
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Fpga Verilog Vhdl Systemverilog Synthesis
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Python Verilator Projects

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Verilator

  1. edalize

    An abstraction library for interfacing EDA tools

  2. AppSignal

    AppSignal knows why the f*#k it crashed. Stop vibe-debugging. Every exception, every backtrace, grouped so you see patterns, not noise.

    AppSignal logo

  3. fpga-sim

    Run students' Verilog designs interactively on a virtual FPGA board

    Project mention: Show HN: FPGA-SIM – interactive virtual boards to help teach Verilog | news.ycombinator.com | 2026-07-08
NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

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Index

# Project Stars
1 edalize 802
2 fpga-sim 6

Sponsored
AppSignal knows why the f*#k it crashed.
Stop vibe-debugging. Every exception, every backtrace, grouped so you see patterns, not noise.
www.appsignal.com

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