neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL. (by stnolting)
ghdl
VHDL 2008/93/87 simulator (by ghdl)
| neorv32-verilog | ghdl | |
|---|---|---|
| 5 | 26 | |
| 40 | 2,223 | |
| - | 1.8% | |
| 8.1 | 9.8 | |
| 6 days ago | 4 days ago | |
| Verilog | VHDL | |
| BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 only |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
neorv32-verilog
Posts with mentions or reviews of neorv32-verilog.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-10-10.
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Converting VHDL to Verilog using GHDL
I am not sure if this helps, but here is a project that also uses GHDL to convert a quite large VHDL setup (including package files) to Verilog: https://github.com/stnolting/neorv32-verilog
- Convert VHDL to Verilog using GHDL (using a RISC-V core as example)
- Show HN: Convert VHDL to Verilog using GHDL (+ first evaluation)
ghdl
Posts with mentions or reviews of ghdl.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-03-30.
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GHDL on mac m1
I downloaded https://github.com/ghdl/ghdl/releases/download/v3.0.0/ghdl-macos-11-mcode.tgz and extracted it to home directory ~.
- How to compile ghdl
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Is the VHDL standard library not publicly available?
The body is here.
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Help on trying to find a FOSS solution to replace Quartus in my class.
GHDL + gtkwave
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If someone is good at programming languages like C, will they be good at description languages like VHDL?
Also, VHDL has its roots in Ada, not Pascal. (In fact, the ghdl simulation tool is written in Ada.)
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What is the netlist file format?
If the goal is simulation, the output of the process is something that can be processed by a standard compiler (like gcc or llvm) or executed by a pseudocode interpreter. See, for example, what is done by ghdl.
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Converting VHDL to Verilog using GHDL
Maybe you could try to minimize your example to a MWE (minimum working example that demonstrates the issue) and then do a bug report against GHDL at https://github.com/ghdl/ghdl/issues
Try a question here: https://github.com/ghdl/ghdl/issues . I have only used GHDL for VHDL, and it worked well for what I was doing with it, but the creator/chief maintainer(?) (Tristan Gingold) should be able to set your issue straight in a short while, and he is pretty active on github.
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Trouble with GHDL and GCC
Find something newer here.
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ghdl, how to include math_real?
replying to myself: I just installed this nightly on a Win10 box and it seems to "work" based on minimal tests. Note that you need to install MinGW.
What are some alternatives?
When comparing neorv32-verilog and ghdl you can also consider the following projects:
biriscv - 32-bit Superscalar RISC-V CPU
logisim-evolution - Digital logic design tool and simulator
riscv - RISC-V CPU Core (RV32IM)
rust_hdl
serv - SERV - The SErial RISC-V CPU
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
naja - Structural Netlist API (and more) for EDA post synthesis flow development
awesome-ada - A curated list of awesome resources related to the Ada and SPARK programming language
edalize - An abstraction library for interfacing EDA tools
gtkwave - GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
VHDL-Guide - VHDL Guide
ASFML - Ada binding to the SFML library