ghdl VS vunit

I downloaded https://github.com/ghdl/ghdl/releases/download/v3.0.0/ghdl-macos-11-mcode.tgz and extracted it to home directory ~.

The body is here.

GHDL + gtkwave

Also, VHDL has its roots in Ada, not Pascal. (In fact, the ghdl simulation tool is written in Ada.)

If the goal is simulation, the output of the process is something that can be processed by a standard compiler (like gcc or llvm) or executed by a pseudocode interpreter. See, for example, what is done by ghdl.

Maybe you could try to minimize your example to a MWE (minimum working example that demonstrates the issue) and then do a bug report against GHDL at https://github.com/ghdl/ghdl/issues

Try a question here: https://github.com/ghdl/ghdl/issues . I have only used GHDL for VHDL, and it worked well for what I was doing with it, but the creator/chief maintainer(?) (Tristan Gingold) should be able to set your issue straight in a short while, and he is pretty active on github.

Find something newer here.

replying to myself: I just installed this nightly on a Win10 box and it seems to "work" based on minimal tests. Note that you need to install MinGW.

My goto tools for verification in VHDL are UVVM and VUnit

I think the VUnit vivado example (https://github.com/VUnit/vunit/tree/master/examples/vhdl/vivado) may be a good starting point when working with Xilinx IP outside of an IDE.

I learned a lot from https://vunit.github.io/ I even became a better VHDL engineer from this fantastic project. It showed me things I did not know VHDL was capable of.

Hey! I haven't seen anyone mention Vunit yet. Vunit has a verification components library with Master and Slave components for a decent amount of buses: Axi, Axi stream, Wishbone, Avalon, Uart. The code isn't 100% bullet proof but it is really useful for testing designs.

I agree vunit is great but due to circumstances (you can see post above) I need the testbench to be purely SV (and vunit as you said wouldn't help with all of that, only some of it, as you have pointed out). When I refered to vunit I forgot to link the example: https://github.com/VUnit/vunit/tree/master/examples/verilog/uart/src . I referred more to tge fact it is self checking, and the tasks can be reused in ither tbs as well

As for simulation, the last time I used it there were a lot of features not supported. Not sure where this is documented, but I know VUnit can't support it per https://github.com/VUnit/vunit/issues/209 .

Please consider adding simulator support to this comparison. For example, Vivado's xsim can't be used with VUnit.

I think these two examples can help you get started. https://github.com/VUnit/vunit/tree/master/examples/vhdl/array_axis_vcs https://github.com/VUnit/vunit/tree/master/examples/vhdl/generate_tests/