Reference of verification IPs

• SVA-AXI4-FVIP

  3 20 10.0 SystemVerilog

  YosysHQ SVA AXI Properties

  

Unfortunately, if you read their documentation, it looks like someone abandoned the project in a state of partial completion. As an example, check out the properties for the W* channel, found on page 51. Notice how many signals have, "No properties for AXI4-Lite, WIP" listed there. It's not just on that page either.

• wb2axip

  51 433 3.1 Verilog

  Bus bridges and other odds and ends

The worst thing that can happen on a bus is a protocol error that causes the device to lock up. Sadly, such errors have been common when using AXI or AXI-Lite--especially since traditional "verification IP" bus models won't catch all circumstances. This is why I make a general (personal) rule that nothing should touch a bus unless it has been formally verified. This check basically guarantees that every bus request gets one (and only one) response. It's not sufficient to verify an IP fully, but it's a good start. You can find my formal verification models for AXI-Lite, Wishbone, and (to some extent) Avalon in this repository. I've also been known to make my full AXI model available to Patreon sponsors of my blog.

• InfluxDB

  www.influxdata.com sponsored

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• blob

  1 - -

Just getting a response from the bus does nothing to tell you if you are getting the right response from the bus. For this reason, I use a special register verification checker. You can read about it here, and find the source in the same repository as I mentioned above.

• AXI4

  4 101 7.5 VHDL

  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

  

• vunit

  10 682 8.2 VHDL

  VUnit is a unit testing framework for VHDL/SystemVerilog

  

Hey! I haven't seen anyone mention Vunit yet. Vunit has a verification components library with Master and Slave components for a decent amount of buses: Axi, Axi stream, Wishbone, Avalon, Uart. The code isn't 100% bullet proof but it is really useful for testing designs.

• WorkOS

  workos.com sponsored

  The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

  

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