VHDL osvvm

Open-source VHDL projects categorized as osvvm
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Topics: Simulation Vhdl Verification simulation-modeling Axi4
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VHDL osvvm Projects

  • AXI4

    AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

VHDL osvvm related posts

  • I made an AXI introduction video! including an AXI-Lite master read and write example!

    2 projects | /r/FPGA | 2 Feb 2023

  • Reference of verification IPs

    7 projects | /r/FPGA | 2 Nov 2022

  • Verilog Text Book Recommendations?

    3 projects | /r/Verilog | 15 Feb 2022

Index

Project Stars
1 AXI4 103

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