vunit VS AXI4

Compare vunit vs AXI4 and see what are their differences.

vunit

VUnit is a unit testing framework for VHDL/SystemVerilog (by VUnit)
Vhdl Verification systemverilog-hdl unit-testing Fpga Asic testbench universal-verification-methodology verilog-hdl
Source Code
vunit.github.io
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AXI4

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components (by OSVVM)
osvvm Axi4 axi4-lite axi4-stream Verification Vhdl vip verification-component tlm testbench Simulation simulation-modeling
Source Code
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vunit AXI4
10 4
682 101
2.1% -
8.2 7.5
28 days ago 19 days ago
VHDL VHDL
GNU General Public License v3.0 or later GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

vunit

Posts with mentions or reviews of vunit. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-02-11.
  • Software languages vs HDLs for verification
    3 projects | /r/FPGA | 11 Feb 2023
    My goto tools for verification in VHDL are UVVM and VUnit
  • Libero - Inefficient Simulations
    1 project | /r/FPGA | 29 Jan 2023
    I think the VUnit vivado example (https://github.com/VUnit/vunit/tree/master/examples/vhdl/vivado) may be a good starting point when working with Xilinx IP outside of an IDE.
  • Books About Testing and Verification
    2 projects | /r/FPGA | 25 Jan 2023
    I learned a lot from https://vunit.github.io/ I even became a better VHDL engineer from this fantastic project. It showed me things I did not know VHDL was capable of.
  • A couple of questions for the experts
    2 projects | /r/FPGA | 22 Dec 2022
  • Reference of verification IPs
    7 projects | /r/FPGA | 2 Nov 2022
    Hey! I haven't seen anyone mention Vunit yet. Vunit has a verification components library with Master and Slave components for a decent amount of buses: Axi, Axi stream, Wishbone, Avalon, Uart. The code isn't 100% bullet proof but it is really useful for testing designs.
  • SystemVerilog testbench library
    1 project | /r/FPGA | 14 Sep 2022
    I agree vunit is great but due to circumstances (you can see post above) I need the testbench to be purely SV (and vunit as you said wouldn't help with all of that, only some of it, as you have pointed out). When I refered to vunit I forgot to link the example: https://github.com/VUnit/vunit/tree/master/examples/verilog/uart/src . I referred more to tge fact it is self checking, and the tasks can be reused in ither tbs as well
  • The Vivado 2021.2 is out thread
    1 project | /r/FPGA | 9 Nov 2021
    As for simulation, the last time I used it there were a lot of features not supported. Not sure where this is documented, but I know VUnit can't support it per https://github.com/VUnit/vunit/issues/209 .
  • How do you do automated testing of your HDL?
    1 project | /r/FPGA | 16 Jun 2021
  • VHDL Testbench Library Comparison
    2 projects | /r/FPGA | 8 Apr 2021
    Please consider adding simulator support to this comparison. For example, Vivado's xsim can't be used with VUnit.
  • The simplest way to automate my testbench?
    1 project | /r/FPGA | 21 Jan 2021
    I think these two examples can help you get started. https://github.com/VUnit/vunit/tree/master/examples/vhdl/array_axis_vcs https://github.com/VUnit/vunit/tree/master/examples/vhdl/generate_tests/

AXI4

Posts with mentions or reviews of AXI4. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-02-02.

What are some alternatives?

When comparing vunit and AXI4 you can also consider the following projects:

spi-fpga - SPI master and SPI slave for FPGA written in VHDL

ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

ghdl - VHDL 2008/93/87 simulator

rust_hdl

upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0

spi-to-axi-bridge - An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

catapult-v3-smartnic-re - Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)

OsvvmLibraries - Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.

wb2axip - Bus bridges and other odds and ends

fpga_puf - :key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL

vunit vs spi-fpga AXI4 vs ravenoc vunit vs ghdl AXI4 vs rust_hdl vunit vs upduino-projects AXI4 vs spi-to-axi-bridge vunit vs catapult-v3-smartnic-re AXI4 vs spi-fpga vunit vs OsvvmLibraries AXI4 vs wb2axip vunit vs fpga_puf AXI4 vs forth-cpu