AXI4
forth-cpu
| AXI4 | forth-cpu | |
|---|---|---|
| 4 | 2 | |
| 103 | 315 | |
| 5.0% | - | |
| 7.6 | 2.6 | |
| 22 days ago | about 2 years ago | |
| VHDL | VHDL | |
| GNU General Public License v3.0 or later | - |
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AXI4
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I made an AXI introduction video! including an AXI-Lite master read and write example!
OSVVM also has an AXI4 VC/VIP. See https://github.com/OSVVM/OsvvmLibraries and for AXI4 specifically see: https://github.com/OSVVM/Axi4
- Reference of verification IPs
- Verilog Text Book Recommendations?
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Entity Input Ports
If you are looking for an AXI Subordinate (new AXI spec names) Memory, you may wish to look at the one from OSVVM (it is free open source (FOSS)). You will find it at: https://github.com/OSVVM/AXI4/blob/master/Axi4/src/Axi4Memory.vhd
forth-cpu
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Designs targeting specific boards?
Like in my head I thought having a piece of verilog and having enough LUTs in any board would do the thing, so what meant here? An example https://github.com/howerj/forth-cpu mentions that the target board is a specific Xilinx.
- Forth SoC Written in VHDL
What are some alternatives?
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
rust_hdl
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
spi-to-axi-bridge - An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
fpga-toolchain - Multi-platform nightly builds of open source FPGA tools
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
sdram-fpga - A FPGA core for a simple SDRAM controller.
wb2axip - Bus bridges and other odds and ends
fpga-fft - A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm