AXI4
vunit
AXI4 | vunit | |
---|---|---|
4 | 10 | |
103 | 682 | |
5.0% | 0.9% | |
7.6 | 8.2 | |
22 days ago | about 1 month ago | |
VHDL | VHDL | |
GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
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AXI4
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I made an AXI introduction video! including an AXI-Lite master read and write example!
OSVVM also has an AXI4 VC/VIP. See https://github.com/OSVVM/OsvvmLibraries and for AXI4 specifically see: https://github.com/OSVVM/Axi4
- Reference of verification IPs
- Verilog Text Book Recommendations?
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Entity Input Ports
If you are looking for an AXI Subordinate (new AXI spec names) Memory, you may wish to look at the one from OSVVM (it is free open source (FOSS)). You will find it at: https://github.com/OSVVM/AXI4/blob/master/Axi4/src/Axi4Memory.vhd
vunit
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Software languages vs HDLs for verification
My goto tools for verification in VHDL are UVVM and VUnit
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Libero - Inefficient Simulations
I think the VUnit vivado example (https://github.com/VUnit/vunit/tree/master/examples/vhdl/vivado) may be a good starting point when working with Xilinx IP outside of an IDE.
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Books About Testing and Verification
I learned a lot from https://vunit.github.io/ I even became a better VHDL engineer from this fantastic project. It showed me things I did not know VHDL was capable of.
- A couple of questions for the experts
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Reference of verification IPs
Hey! I haven't seen anyone mention Vunit yet. Vunit has a verification components library with Master and Slave components for a decent amount of buses: Axi, Axi stream, Wishbone, Avalon, Uart. The code isn't 100% bullet proof but it is really useful for testing designs.
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SystemVerilog testbench library
I agree vunit is great but due to circumstances (you can see post above) I need the testbench to be purely SV (and vunit as you said wouldn't help with all of that, only some of it, as you have pointed out). When I refered to vunit I forgot to link the example: https://github.com/VUnit/vunit/tree/master/examples/verilog/uart/src . I referred more to tge fact it is self checking, and the tasks can be reused in ither tbs as well
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The Vivado 2021.2 is out thread
As for simulation, the last time I used it there were a lot of features not supported. Not sure where this is documented, but I know VUnit can't support it per https://github.com/VUnit/vunit/issues/209 .
- How do you do automated testing of your HDL?
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VHDL Testbench Library Comparison
Please consider adding simulator support to this comparison. For example, Vivado's xsim can't be used with VUnit.
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The simplest way to automate my testbench?
I think these two examples can help you get started. https://github.com/VUnit/vunit/tree/master/examples/vhdl/array_axis_vcs https://github.com/VUnit/vunit/tree/master/examples/vhdl/generate_tests/
What are some alternatives?
ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
rust_hdl
ghdl - VHDL 2008/93/87 simulator
spi-to-axi-bridge - An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
catapult-v3-smartnic-re - Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
wb2axip - Bus bridges and other odds and ends
OsvvmLibraries - Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
fpga_puf - :key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.