Top 4 VHDL Xilinx Projects

neorv32-setups

5 52 8.7 VHDL

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Project mention: How to find the pin mapping for connecting Zybo Z7-20 or Nexyx A7 board to a computer over USB-JTAG? | /r/FPGA | 2023-08-03

Hello. In my project, I am trying to run NEORV32 processor in an FPGA. My plan is to perform debugging of the design over JTAG after running it on an FPGA. I currently have a Zybo Z7-20 and a Nexyx A7 board at hand. As per my understanding, for both of the boards, I need to find the board pins associated with JTAG and manually connect them through the constraint file. I was going through the reference manuals for both FPGAs but couldn't find the pins that need to be connected.

kvm-ip-zynq

2 19 0.0 VHDL

KVM over IP Gateway targeting Zynq-7000 SoC
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SoC

1 11 1.1 VHDL

Github Repo for Embedded FPGA course by Vincent Claes
Xilinx-DPUV3.0-Vivado-Proj

1 3 2.6 VHDL

Deep Learning Processing Unit (DPU IP) integration with Application Processing Unit (APU) using (Zynq-7000 PS) in Xilinx Vivado Design Suite

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2023-08-03.