DSP

Digital Signal Processing Library for Xilinx Platforms. Digital IIR/FIR filters, GHz rate non-linear pulse fitting, and data acquisition systems. (by Vestaia)

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NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better DSP alternative or higher similarity.

DSP reviews and mentions

Posts with mentions or reviews of DSP. We have used some of these posts to build our list of alternatives and similar projects.
  • Data not being processed by custom Verilog filtering module?
    1 project | /r/FPGA | 8 Jun 2023
    Right now I have a trapezoidal filter core (written in Verilog) created by a colleague that I know has been used with success in the past. So, starting from a simple ADC to DAC project provided by another Red Pitaya user, Pavel (here), I placed the core into the block design in between the ADC and DAC as such, let Vivado do its thing, and generated a bitstream without error (note that trap_0 has S00_AXIS data width 16, so it only takes the 16 LSB from the ADC, which I believe is from adc_dat_a_i). All of the source code for the trapezoidal filter core can be found on GitHub (top core and dependencies).

Stats

Basic DSP repo stats
1
0
10.0
almost 2 years ago

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