Data not being processed by custom Verilog filtering module?

• DSP

  1 0 10.0 VHDL

  Digital Signal Processing Library for Xilinx Platforms. Digital IIR/FIR filters, GHz rate non-linear pulse fitting, and data acquisition systems. (by Vestaia)

Right now I have a trapezoidal filter core (written in Verilog) created by a colleague that I know has been used with success in the past. So, starting from a simple ADC to DAC project provided by another Red Pitaya user, Pavel (here), I placed the core into the block design in between the ADC and DAC as such, let Vivado do its thing, and generated a bitstream without error (note that trap_0 has S00_AXIS data width 16, so it only takes the 16 LSB from the ADC, which I believe is from adc_dat_a_i). All of the source code for the trapezoidal filter core can be found on GitHub (top core and dependencies).

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