Intel discontinues Nios II IP

This page summarizes the projects mentioned and recommended in the original post on /r/FPGA

InfluxDB - Power Real-Time Data Analytics at Scale
Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
www.influxdata.com
featured
SaaSHub - Software Alternatives and Reviews
SaaSHub helps you find the best software and product alternatives
www.saashub.com
featured
  • VexRiscv

    A FPGA friendly 32 bit RISC-V CPU implementation

    I don't get what's going on with licensing and device support. I'm missing something here perhaps, but we use Cyclone 10 GX onwards and Quartus Pro so I don't have enough context maybe. Have you considered swapping your Nios ii to a VexRISCV as a side note? At ~1 Dhrystone MIPS/MHz it's roughly double that of the Nios V, for very few resources. All open source too. None of the migration documentation support though, so I can't judge how hard it would be.

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

    InfluxDB logo
  • bonfire-cpu

    FPGA optimized RISC-V (RV32IM) implemenation

    My team has a solution in place already, which was to write all of our floating point code to call macros rather than putting arithmetic in the code. This allowed us to port easily to an RV32IM CPU (a fork of this one) then memory map an FPU onto it, the macros were then changed to atomically access the FPU registers for any floating point arithmetic. In Intel chips we are using the Nios II floating point hardware 2 (which can be instantiated separately), in other vendors we use a combination of operators from the Opencores FPU and this one, depending upon what operators are selected via generics, the maths library will pick up what configuration is used and choose the available operators.

  • fpu-sp

    IEEE 754 floating point library in system-verilog and vhdl

    My team has a solution in place already, which was to write all of our floating point code to call macros rather than putting arithmetic in the code. This allowed us to port easily to an RV32IM CPU (a fork of this one) then memory map an FPU onto it, the macros were then changed to atomically access the FPU registers for any floating point arithmetic. In Intel chips we are using the Nios II floating point hardware 2 (which can be instantiated separately), in other vendors we use a combination of operators from the Opencores FPU and this one, depending upon what operators are selected via generics, the maths library will pick up what configuration is used and choose the available operators.

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

Suggest a related project

Related posts

  • Looking for help with RISC-V softcore and VHDL

    3 projects | /r/FPGA | 20 Apr 2022
  • Show HN: Soft-core RISC-V SoC with gdb support

    2 projects | news.ycombinator.com | 31 May 2021
  • RISC-V with AXI Peripheral

    2 projects | /r/FPGA | 20 Jun 2023
  • How Much Would It Cost For A Truly Open Source RISC-V SOC?

    5 projects | /r/RISCV | 14 Jan 2023
  • Which FPGA for getting into RISC-V?

    2 projects | /r/RISCV | 1 Dec 2022