Show HN: Soft-core RISC-V SoC with gdb support

• neorv32

  77 1,423 9.9 C

  :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

• VexRiscv

  21 2,252 7.6 Assembly

  A FPGA friendly 32 bit RISC-V CPU implementation

  

The SmallAndProductive configuration can be found here: https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/s....

It’s a basic R32I configuration, without traps or branch prediction enabled, but with 5 pipeline stages and all bypass paths included, so it executes straight code at 1 instruction per clock.

The VexRiscv also comes with a bunch of SOCs etc.

The amazing thing about the VexRiscv is that it is configurable to the extreme and it’s extremely easy to do so. There are tons of other configurations in the same directory. It’d be trivial to create one that has the same configuration as this one and compare.

SpinalHDL supports both Verilog and VHDL output, so you’re covered there as well.

It’s not native VHDL, of course, so if you want to understand the code at the VHDL level instead of just wanting to use a soft core CPU, it’s probably not for you.

That said, the VexRiscv design methodology is pretty amazing as well. I wrote about it here:

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