RISC-V with AXI Peripheral

This page summarizes the projects mentioned and recommended in the original post on /r/FPGA
soc Fpga Vhdl Verilog Riscv

InfluxDB
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  • neorv32-setups

    📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

  • VexRiscv

    A FPGA friendly 32 bit RISC-V CPU implementation

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

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NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

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