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Neorv32 Alternatives
Similar projects and alternatives to neorv32
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InfluxDB
Access the most powerful time series database as a service. Ingest, store, & analyze all types of time series data in a fully-managed, purpose-built database. Keep data forever with low-cost storage and superior data compression.
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upduino-projects
Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
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chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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SonarLint
Clean code begins in your IDE with SonarLint. Up your coding game and discover issues early. SonarLint is a free plugin that helps you find & fix bugs and security issues from the moment you start writing code. Install from your favorite IDE marketplace today.
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vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
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neorv32-setups
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
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cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
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SaaSHub
SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives
neorv32 reviews and mentions
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Recommendations for RISC-V on FPGA
How about NEORV32?
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SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though
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Anyone want to share some embedded projects they have done?
Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32
- Mapping compressed 'C' instructions to their 32b counterparts.
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Uploading software program to a custom processor design on a Nexys A7
https://github.com/stnolting/neorv32 ;)
- A tiny and open-source (BSD) RISC-V SoC for (all!) FPGAs
- Looking for help with RISC-V softcore and VHDL
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Risc-v rv32i softcore processor for Zybo-z7-10
How about the NEORV32?
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RISC-V Verilog tutorials
This VHDL RISC-V SoC has a lot of documentation: https://github.com/stnolting/neorv32
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How to verify Embench Benchmark in a RISC-V core?
I am not sure about Embench, but you could start with "porting" CoreMark as there are several implementations out there (like this one).
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A note from our sponsor - InfluxDB
www.influxdata.com | 22 Mar 2023
Stats
stnolting/neorv32 is an open source project licensed under BSD 3-clause "New" or "Revised" License which is an OSI approved license.