Neorv32 Alternatives

Similar projects and alternatives to neorv32

• VexRiscv

  4 1,830 6.8 Assembly neorv32 VS VexRiscv

  A FPGA friendly 32 bit RISC-V CPU implementation

  

• linux-on-litex-vexriscv

  1 428 6.0 Python neorv32 VS linux-on-litex-vexriscv

  Linux on LiteX-VexRiscv

  

• InfluxDB

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• picoMIPS

  - 1 0.0 SystemVerilog neorv32 VS picoMIPS

  picoMIPS processor doing affine transformation

• upduino-projects

  - 6 2.5 VHDL neorv32 VS upduino-projects

  Various VHDL projects I've worked on for the Upduino v2.0 and v3.0

• chipyard

  - 1,035 7.5 C neorv32 VS chipyard

  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

  

• fpga-zynq

  - 352 0.0 Tcl neorv32 VS fpga-zynq

  Support for Rocket Chip on Zynq FPGAs

  

• wb2axip

  1 339 4.8 Verilog neorv32 VS wb2axip

  Bus bridges and other odds and ends

• SonarLint

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• linux-on-litex-rocket

  - 56 1.0 neorv32 VS linux-on-litex-rocket

  Run 64-bit Linux on LiteX + RocketChip

  

• litex

  3 2,033 9.3 C neorv32 VS litex

  Build your hardware, easily!

• serv

  1 941 6.1 Verilog neorv32 VS serv

  SERV - The SErial RISC-V CPU

• picorv32

  2 2,335 0.0 Verilog neorv32 VS picorv32

  PicoRV32 - A Size-Optimized RISC-V CPU

  

• vivado-risc-v

  2 419 6.5 C neorv32 VS vivado-risc-v

  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

• riscv-arch-test

  2 363 6.6 Assembly neorv32 VS riscv-arch-test

  

• Rudi-RV32I

  2 88 0.0 VHDL neorv32 VS Rudi-RV32I

  A rudimental RISCV CPU supporting RV32I instructions, in VHDL

• neorv32-setups

  2 30 7.3 VHDL neorv32 VS neorv32-setups

  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

• cva6

  1 1,682 8.4 SystemVerilog neorv32 VS cva6

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  

• riscv-asm-manual

  1 1,091 3.0 neorv32 VS riscv-asm-manual

  RISC-V Assembly Programmer's Manual

  

• fusesoc

  1 940 8.9 Python neorv32 VS fusesoc

  Package manager and build abstraction tool for FPGA/ASIC development

• ibex

  1 939 8.2 SystemVerilog neorv32 VS ibex

  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

  

• black-parrot

  1 382 5.8 SystemVerilog neorv32 VS black-parrot

  A Linux-capable RISC-V multicore for and by the world

  

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