rp32
neorv32
| rp32 | neorv32 | |
|---|---|---|
| 3 | 77 | |
| 8 | 1,429 | |
| - | - | |
| 5.9 | 9.9 | |
| 8 months ago | 6 days ago | |
| SystemVerilog | C | |
| Apache License 2.0 | BSD 3-clause "New" or "Revised" License |
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rp32
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How to design a more elegant and simple instraction decoder
Here is my decoder: https://github.com/jeras/rp32/blob/master/hdl/rtl/riscv/riscv_isa_i_pkg.sv
- Mapping compressed 'C' instructions to their 32b counterparts.
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Is a single cycle CPU of any use besides learning?
I am writing a RISC-V core with a strict IPC=1 (instructions per cycle). One piece is still in my mind, but the CPU is already passing instruction set tests.https://github.com/jeras/rp32The code was not properly synthesized yet, and there is almost no documentation, if you wish to use anything, but do not know how to, you can ask for help as a GitHub issue. But I do not know how much time I will have to answer.
neorv32
- An example of how to add the A ISA extension's LR/SC operations into an open-source architecture
- NEORV32 - A tiny, customizable and highly extensible MCU-class 32-bit RISC-V microcontroller-like SoC written in platform-independent VHDL
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Recommendations for RISC-V on FPGA
How about NEORV32?
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SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though
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RISCV CPU using PL on Pynq Z2 Development Board
NEORV32 is an open source soft core and very well documented. I would recommend you to take a look at it and play around a bit. And it is certainly possible to have a soft core running on only the PL side without PS interference.
- A tiny 1-Wire controller for FPGAs (in VHDL)
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Anyone want to share some embedded projects they have done?
Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32
What are some alternatives?
riscv-formal - RISC-V Formal Verification Framework
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
friscv - RISCV CPU implementation in SystemVerilog
picoMIPS - picoMIPS processor doing affine transformation
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
Cores-VeeR-EH1 - VeeR EH1 core
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
simple-riscv - A simple three-stage RISC-V CPU
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set