Recommendations for RISC-V on FPGA

• cva6

  2 1,731 7.9 SystemVerilog

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  

  Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?

• rocket-chip

  2 2,617 0.0 Scala

  Rocket Chip Generator

  

  Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?

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• vivado-risc-v

  4 478 5.4 C

  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

  Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?

• r5lite

  1 - -

  I wish I could recommend the one I am working on open-sourcing, but it's not exactly ready yet for a school project (shameless plug for the future: https://gitlab.com/specbranch/r5lite/) unless you are doing something very basic solely inside the core.

• iob-soc-opencryptolinux

  3 8 10.0 Tcl

  

  SoC with Vexriscv capable of running Linux: https://github.com/IObundle/iob-soc-opencryptolinux

• iob-soc

  1 105 10.0 Tcl

  RISC-V System on Chip Template

  

  SoC with PicoRV32 to run baremetal applications: https://github.com/IObundle/iob-soc

• neorv32

  15 1,151 9.2 VHDL

  🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

  How about NEORV32?

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