neorv32
VexRiscv
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neorv32 | VexRiscv | |
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77 | 21 | |
1,409 | 2,244 | |
- | 3.0% | |
9.9 | 7.6 | |
13 days ago | 14 days ago | |
VHDL | Assembly | |
BSD 3-clause "New" or "Revised" License | MIT License |
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neorv32
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Recommendations for RISC-V on FPGA
How about NEORV32?
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SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though
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Anyone want to share some embedded projects they have done?
Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32
- Mapping compressed 'C' instructions to their 32b counterparts.
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Uploading software program to a custom processor design on a Nexys A7
https://github.com/stnolting/neorv32 ;)
- A tiny and open-source (BSD) RISC-V SoC for (all!) FPGAs
- Looking for help with RISC-V softcore and VHDL
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Risc-v rv32i softcore processor for Zybo-z7-10
How about the NEORV32?
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RISC-V Verilog tutorials
This VHDL RISC-V SoC has a lot of documentation: https://github.com/stnolting/neorv32
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How to verify Embench Benchmark in a RISC-V core?
I am not sure about Embench, but you could start with "porting" CoreMark as there are several implementations out there (like this one).
VexRiscv
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Need help to build a RISC-V Processor on Artix-7 FPGA: Final Year Engineering Project Guide
With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.
- RISC-V with AXI Peripheral
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Intel discontinues Nios II IP
I don't get what's going on with licensing and device support. I'm missing something here perhaps, but we use Cyclone 10 GX onwards and Quartus Pro so I don't have enough context maybe. Have you considered swapping your Nios ii to a VexRISCV as a side note? At ~1 Dhrystone MIPS/MHz it's roughly double that of the Nios V, for very few resources. All open source too. None of the migration documentation support though, so I can't judge how hard it would be.
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How Much Would It Cost For A Truly Open Source RISC-V SOC?
If you use LiteX to generate a VexRiscV system-on-a-chip, you can include an open source DDR DRAM PHY. This works on Xilinx Spartan-6, Spartan7Artix7/Kintex7/Virtex7 FPGAs, and Lattice ECP5 FPGAs. DDR/LPDDR/DDR2/DDR3 depending on the FPGA.
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Which FPGA for getting into RISC-V?
Something like https://github.com/SpinalHDL/VexRiscv will take far fewer
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Looking for a suitable open-source RISC-V for an embedded project
4) https://github.com/SpinalHDL/VexRiscv
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What do think of Chisel HDL? is it worth learning over Verilog/SystemVerilog?
I really like Chisel HDL or any other new HDL languages like SpinalHDL or migen b/c it allows you to create some very complex yet modular designs. See VexRiscv or LiteX for instance. Languages like this exist b/c there is a need for it, but I wouldn't say that you should learn these new languages over verilog. All these languages output verilog/VHDL for now, but there is work being to done eliminate the need for outputting verilog; eventually, Chisel will output an open source CIRCT IR. Hope is to get EDA vendors to support this IR which I'm sure will take a while. For now, you should definitely learn Verilog or VHDL before Chisel.
- Looking for help with RISC-V softcore and VHDL
- Are there any dual-GBE, PoE-capable SBCs?
- Tips on building a RISC-V processor on FPGA
What are some alternatives?
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
picoMIPS - picoMIPS processor doing affine transformation
RISCV-FiveStage - Marginally better than redstone
wb2axip - Bus bridges and other odds and ends
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
fpga-zynq - Support for Rocket Chip on Zynq FPGAs
linux-on-litex-rocket - Run 64-bit Linux on LiteX + RocketChip
serv - SERV - The SErial RISC-V CPU