SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG

This page summarizes the projects mentioned and recommended in the original post on /r/RISCV

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  • neorv32

    :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

  • GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though

  • picorv32

    PicoRV32 - A Size-Optimized RISC-V CPU

  • picorv32 is written in Verilog.

  • WorkOS

    The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

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  • riscv

    Verilog implementation of a RISC-V core (by ataradov)

  • My very simple implementation in Verilog - https://github.com/ataradov/riscv

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

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