PicoRV32 - A Size-Optimized RISC-V CPU (by cliffordwolf)

Picorv32 Alternatives

Similar projects and alternatives to picorv32

NOTE: The number of mentions on this list indicates mentions on common posts. Hence, a higher number means a better picorv32 alternative or higher similarity.

Suggest an alternative to picorv32


Posts where picorv32 has been mentioned. We have used some of these posts to build our list of alternatives and similar projects - the last one was on 2021-04-21.
  • Build a RISC-V CPU from scratch
    news.ycombinator.com | 2021-05-27
    Actually more than one, and new projects are started everyday to RE more architectures as we gathertools and knowledge from previous efforts. While the newer higher end fpgas are still out of reach a Lattice ECP5 can do pciE, gigabit ethernet, hdmi, ddr3, usb3, and of course has more than enough for a RISC-V (as a matter of fact you can fo one in a much cheaper/smaller ice40: https://github.com/cliffordwolf/picorv32
  • RISC-V IP core on an FPGA.
    reddit.com/r/FPGA | 2021-04-21
    I've not used it in anger, but https://github.com/cliffordwolf/picorv32 caught my attention recently - having support for the Atrix-7, coming in various sizes, and calling out specific support for AXI4.
    reddit.com/r/FPGA | 2021-04-21
    While I have to believe there exists a RISC-V core with a good, fast, and working AXI interface, they're unfortunately hard to find. VexRiscv's AXI interface was quite broken when I last examined it. PicoRV's AXI interface should work, but it's nothing to write about. Although PICORV32 is supposed to be able to run at 250MHz, that bus interface is going to cost you a minimum of about 10 clocks per access. See here, Fig 13 for example. Since the PICORV32 uses the same interface for both instruction fetch and memory, you'll likely require 10-20 cycles per instruction for the memory access alone. Add another (rough) 20 cycles per instruction if your CPU is running from DDR3 SDRAM.


Basic picorv32 repo stats
3 months ago