Picorv32 Alternatives

picorv32 reviews and mentions

• Ask HN: Going low-level – what to learn next?
  5 projects | news.ycombinator.com | 4 Jun 2024

  FPGA + a RISC-V core. There are loads around, the simplest is probably https://github.com/YosysHQ/picorv32

  Learn how it works, try adding a new instruction or implementing an extension.

• RISC-V support in Android just got a big setback
  4 projects | news.ycombinator.com | 30 Apr 2024

  > Right now, most devices on the market do not support the C extension

  This is not true and easily verifiable.

  The C extension is defacto required, the only cores that don't support it are special purpose soft cores.

  C extension in the smallest IP available core https://github.com/olofk/serv?tab=readme-ov-file

  Supports M and C extensions https://github.com/YosysHQ/picorv32

  Another sized optimized core with C extension support https://github.com/lowrisc/ibex

  C extension in the 10 cent microcontroller https://www.wch-ic.com/products/CH32V003.html

  This one should get your goat, it implements as much as it can using only compressed instructions https://github.com/gsmecher/minimax

• SPI PROTOCOL in FPGA
  1 project | /r/FPGA | 14 May 2023

  In contrast to most people here saying you NEED to spend money. I disagree with that. You can implement and simulate a SPI master/slave fully on your computer, no FPGA or other hardware required. There are simulation models for SPI peripherals you could use. For example: https://github.com/YosysHQ/picorv32/blob/master/picosoc/spiflash.v

• How many gates does a decent risc-v implementation take?
  2 projects | /r/RISCV | 16 Feb 2023

  The Pico RV32 is pretty small, and can go as low as about 750 LUTs, with most features elided. I don't know how Xilinix LUTs translate to Lattice though.

• Open-source RISC-V CPU projects for contribution
  8 projects | /r/RISCV | 28 Jan 2023

  Picorv32: https://github.com/YosysHQ/picorv32

• We ran a Unix-like OS (Xv6) on our home-built CPU with our home-built C compiler
  3 projects | news.ycombinator.com | 27 Nov 2022

  There are loads of free RISC-V cores that you can read the source of and run on cheap FPGAs. Take a look at PicoRV32: https://github.com/YosysHQ/picorv32

• SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
  3 projects | /r/RISCV | 26 Nov 2022

  picorv32 is written in Verilog.

• Minimax: a Compressed-First, Microcoded RISC-V CPU
  4 projects | /r/FPGA | 26 Oct 2022

  In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.

• Apple to Move a Part of Its Embedded Cores to RISC-V
  4 projects | news.ycombinator.com | 16 Sep 2022

  That is, reducing the number of LUT required to implement a CPU of a given ISA.

  A basic RV32 CPU is down to 500-700 LUT.

      https://github.com/YosysHQ/picorv32

• Designing a reasonable memory interface
  1 project | /r/FPGA | 8 Aug 2022

  I've bought a cheap FPGA board (Sipeed Tang Nano 9K) because I want to implement a little 8 or 16-bit CPU. The FPGA has plenty of BRAM for such a little CPU, so I wouldn't even need to implement an SPI controller initially, but I want to implement a von Neumann architecture, and was wondering if the only way of doing so using single port (or semi dual port) RAM would be to use 2 cycles or more for memory transfer operations (one for loading the instruction, one for executing the actual memory transfer), or if there was any technique that could be used to avoid this without having to implement instruction-level parallelism. Even if not, references to understandable code implementing a simple memory interface would be appreciated. I looked at PicoRV32 but couldn't really understand its inner workings.

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