minimax

Minimax: a Compressed-First, Microcoded RISC-V CPU (by gsmecher)

Minimax Alternatives

Similar projects and alternatives to minimax

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better minimax alternative or higher similarity.

minimax reviews and mentions

Posts with mentions or reviews of minimax. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-08-04.
  • A Single-Cycle 64-Bit RISC-V Register File
    2 projects | news.ycombinator.com | 4 Aug 2023
    On FPGAs, a register file probably fits better into distributed RAM than block RAM.

    On Xilinx, for example: a 64-bit register file doesn't map efficiently to Xilinx's RAMB36 primitives. You'd need 2 RAMB36 primitives to provide a 64-bit wide memory with 1 write port and 2 read ports, each addressed separately. Only 6% (32 of 512) entries in each RAMB36 are ever addressable. It's this inefficient because ports, not memory cells, are the contented resource and BRAMs geometries aren't that elastic.

    A 64-bit register file in distributed RAM, conversely, is a something like an array of DPRAM32 primitives (see, for example, UG474). Each register would still be stored multiple times to provide additional ports, but depending on the fabric, there's less (or no) unaddressed storage cells.

    The Minimax RISC-V CPU (https://github.com/gsmecher/minimax; advertisement warning: my project) is what you get if you chase efficient mapping of FPGA memory primitives (both register-file and RAM) to a logical conclusion. Whether this is actually worth hyper-optimizing really depends on the application. Usually, it's not.

  • Verilator - Do I need to maintain two testbench suits?
    2 projects | /r/FPGA | 10 Jul 2023
    I haven't used it on a huge design (I'm usually a VHDL person), but it was a hassle-free replacement for iverilog when regression testing Minimax. Performance is substantially better; compilation times are worse.
  • Zylin ZPU: The worlds smallest 32 bit CPU with GCC toolchain
    7 projects | news.ycombinator.com | 13 Apr 2023
    Note that you can't compare LUT4 results (ZPU @ 440 LUTs) against LUT6 results (PicoRV32 @ 750 LUTs). The ZPU is remarkably small, and it's a bigger gap than a direct comparison shows.

    SERV is a fair comparison, since it's architected for 4LUTs and I suspect the synthesis results come from iCE40 tools.

    I have a contender in the "very small" space, too [1], although I don't claim it's as mature or complete as SERV. (If Minimax was excluded from your post on the basis of insanity, I'm OK with that.)

    [1] https://github.com/gsmecher/minimax

  • Senior Design Project Ideas?
    4 projects | /r/FPGA | 21 Jan 2023
    I develop Minimax (https://github.com/gsmecher/minimax), an open-source RISC-V implementation. It's currently written in both VHDL and Verilog (the two implementations are equivalent, though I am likely to drop the VHDL implementation if it's too much work to keep them both.)
  • Compiled and Interpreted Languages: Two Ways of Saying Tomato
    4 projects | news.ycombinator.com | 11 Jan 2023
  • PicoBlaze in Verilog / Vivado
    2 projects | /r/FPGA | 16 Nov 2022
    The best point-of-entry for "tiny" MCUs these days is FemtoRV32-Quark or SERV. I also maintain my own small RISC-V core (Minimax), though it's early on in graduating from "experiment" to "real design".
  • Minimax: A Compressed-First, Microcoded RISC-V CPU
    2 projects | news.ycombinator.com | 1 Nov 2022
  • Minimax: a Compressed-First, Microcoded RISC-V CPU
    4 projects | /r/FPGA | 26 Oct 2022
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