picorv32
wd65c02
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picorv32 | wd65c02 | |
---|---|---|
15 | 8 | |
2,770 | 26 | |
2.8% | - | |
5.2 | 0.0 | |
about 1 month ago | almost 2 years ago | |
Verilog | SystemVerilog | |
ISC License | GNU General Public License v3.0 only |
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picorv32
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SPI PROTOCOL in FPGA
In contrast to most people here saying you NEED to spend money. I disagree with that. You can implement and simulate a SPI master/slave fully on your computer, no FPGA or other hardware required. There are simulation models for SPI peripherals you could use. For example: https://github.com/YosysHQ/picorv32/blob/master/picosoc/spiflash.v
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How many gates does a decent risc-v implementation take?
The Pico RV32 is pretty small, and can go as low as about 750 LUTs, with most features elided. I don't know how Xilinix LUTs translate to Lattice though.
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Open-source RISC-V CPU projects for contribution
Picorv32: https://github.com/YosysHQ/picorv32
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We ran a Unix-like OS (Xv6) on our home-built CPU with our home-built C compiler
There are loads of free RISC-V cores that you can read the source of and run on cheap FPGAs. Take a look at PicoRV32: https://github.com/YosysHQ/picorv32
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SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
picorv32 is written in Verilog.
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Minimax: a Compressed-First, Microcoded RISC-V CPU
In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.
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Apple to Move a Part of Its Embedded Cores to RISC-V
That is, reducing the number of LUT required to implement a CPU of a given ISA.
A basic RV32 CPU is down to 500-700 LUT.
https://github.com/YosysHQ/picorv32
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Designing a reasonable memory interface
I've bought a cheap FPGA board (Sipeed Tang Nano 9K) because I want to implement a little 8 or 16-bit CPU. The FPGA has plenty of BRAM for such a little CPU, so I wouldn't even need to implement an SPI controller initially, but I want to implement a von Neumann architecture, and was wondering if the only way of doing so using single port (or semi dual port) RAM would be to use 2 cycles or more for memory transfer operations (one for loading the instruction, one for executing the actual memory transfer), or if there was any technique that could be used to avoid this without having to implement instruction-level parallelism. Even if not, references to understandable code implementing a simple memory interface would be appreciated. I looked at PicoRV32 but couldn't really understand its inner workings.
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Risc-v rv32i softcore processor for Zybo-z7-10
Have you looked at PicoRV32? https://github.com/YosysHQ/picorv32
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Need help with implementing a media player using FPGAs ?
What I mean is that you use the FPGA fabric to implement a soft-core CPU, like MicroBlaze (Xilinx) or Nios II (Altera/Intel) or RISC-V or any other CPU you like. Then you can do the MP3 or WAV signal decoding in software, which will be orders of magnitude easier to do than to do it in hardware. For a media player, this is more than adequate.
wd65c02
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Beginner Verilog Testing Question
I'm implementing a 6502. I wrote a test-bench program in Verilog that takes a mem file for the test program, and another for the test-plan, and verifies the CPU's execution against the test plan. You can check it out. Feel free to steal ideas. You can even use the code itself, so long as you honor the GPL it's under. Here is a link to the actual file inside the project.
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Building Ben's 8-bit CPU in VHDL (to learn a bit about FPGAs). Baby Step 1: Clock Module...
I started such a project in VeriLog once, if you want a reference. I abandoned it before getting to branches, however, in favor of writing a 6502 implementation.
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Stages of prototyping a RISC-V processor on an FPGA?
You can look for ideas at my test bench. The testbench is available here. Don't copy any actual code unless you are willing to abide by the GPL, though. I doubt it will help you in the literal way, anyways, as it is built for testing a CISC CPU, so some adaptations will be required no matter how free you are to use the code. I am hoping it will give you some ideas.
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Debugging a timing loop
I have a design (available here) that has loops in the timing report after implementation. The problem is that I cannot seem to trace the nets I'm seeing in the report to my code, and those I did manage to trace seem to be routed through non-blocking assignments. I'm missing something, but I'm not sure what.
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Help with timing constraints
The project source is here.
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Which is better?
So I went through all the files in the wd65c02/wd65c02.srcs/sources_1/new/ directory, but I can't find the code snippets that you're talking about?
- My Verilog 6502 is progressing
What are some alternatives?
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Ben8Bit - Verilog implementation of Ben Eater's 8-bit breadboard computer
neorv32-setups - 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
rocket-chip - Rocket Chip Generator
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Projects - Ted Fried's MicroCore Labs Projects which include microsequencer-based FPGA cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. MCL51, MCL64, MCL65, MCL65+, MCL68, MCL86, MCL86+, MCL86jr, MCLR5, MCLZ8
vivado-risc-v - Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
minimax - Minimax: a Compressed-First, Microcoded RISC-V CPU
openc910 - OpenXuantie - OpenC910 Core
litex - Build your hardware, easily!
FPGA_Multimedia_Player - MSc Final Project