Minimax: a Compressed-First, Microcoded RISC-V CPU

• minimax

  9 146 10.0 Assembly

  Minimax: a Compressed-First, Microcoded RISC-V CPU

• learn-fpga

  13 1,569 8.1 C++

  Learning FPGA, yosys, nextpnr, and RISC-V

  In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.

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• picorv32

  7 2,269 0.0 Verilog

  PicoRV32 - A Size-Optimized RISC-V CPU

  

  In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.

• serv

  10 911 6.5 Verilog

  SERV - The SErial RISC-V CPU

  In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.

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