Minimax: a Compressed-First, Microcoded RISC-V CPU

• minimax

  13 194 5.8 Verilog

  Minimax: a Compressed-First, Microcoded RISC-V CPU

• learn-fpga

  22 2,323 7.3 C++

  Learning FPGA, yosys, nextpnr, and RISC-V

In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.

• InfluxDB

  www.influxdata.com sponsored

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• picorv32

  15 2,763 2.8 Verilog

  PicoRV32 - A Size-Optimized RISC-V CPU

  

In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.

• serv

  19 1,234 7.7 Verilog

  SERV - The SErial RISC-V CPU

In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.

Suggest a related project