picorv32 VS openc910

In contrast to most people here saying you NEED to spend money. I disagree with that. You can implement and simulate a SPI master/slave fully on your computer, no FPGA or other hardware required. There are simulation models for SPI peripherals you could use. For example: https://github.com/YosysHQ/picorv32/blob/master/picosoc/spiflash.v

The Pico RV32 is pretty small, and can go as low as about 750 LUTs, with most features elided. I don't know how Xilinix LUTs translate to Lattice though.

Picorv32: https://github.com/YosysHQ/picorv32

There are loads of free RISC-V cores that you can read the source of and run on cheap FPGAs. Take a look at PicoRV32: https://github.com/YosysHQ/picorv32

picorv32 is written in Verilog.

In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.

That is, reducing the number of LUT required to implement a CPU of a given ISA.

A basic RV32 CPU is down to 500-700 LUT.

    https://github.com/YosysHQ/picorv32

I've bought a cheap FPGA board (Sipeed Tang Nano 9K) because I want to implement a little 8 or 16-bit CPU. The FPGA has plenty of BRAM for such a little CPU, so I wouldn't even need to implement an SPI controller initially, but I want to implement a von Neumann architecture, and was wondering if the only way of doing so using single port (or semi dual port) RAM would be to use 2 cycles or more for memory transfer operations (one for loading the instruction, one for executing the actual memory transfer), or if there was any technique that could be used to avoid this without having to implement instruction-level parallelism. Even if not, references to understandable code implementing a simple memory interface would be appreciated. I looked at PicoRV32 but couldn't really understand its inner workings.

Have you looked at PicoRV32? https://github.com/YosysHQ/picorv32

What I mean is that you use the FPGA fabric to implement a soft-core CPU, like MicroBlaze (Xilinx) or Nios II (Altera/Intel) or RISC-V or any other CPU you like. Then you can do the MP3 or WAV signal decoding in software, which will be orders of magnitude easier to do than to do it in hardware. For a media player, this is more than adequate.

> I'm pretty sure that SiFive isn't allowed to sell their RISC-V core designs to any Chinese company already.

The JH7110 SoC from the Chinese firm Starfive uses SiFive's U74 core. Eswin, also Chinese uses SiFive's P550 core in their upcoming EIC7700 SoC.

> All Chinese RISC-V core designs have been proprietary designs thus far.

There is the OpenC910 [1] and OpenXiangShan [2].

[1] https://github.com/T-head-Semi/openc910

Note that the C910 CPU cores used in this chip are in fact open source:

https://github.com/T-head-Semi/openc910

(C920 is just C910 plus RVV draft 0.7.1 vector unit which pretty much no software uses anyway, sadly)

The Milk-V Pioneer uses a C910 CPU, which has been open sourced by t-head: https://github.com/T-head-Semi/openc910

More precisely, a Chinese university assembled a rack containing 48 [1] commercially available SBCs [2], each with a Chinese-designed and made SG2042 SoC with 64 C910 CPU cores. The C910 was designed in China in 2018/19 and open-sourced in October 2021, on Microsoft's github site.

https://github.com/T-head-Semi/openc910

The SG2042 is the most powerful RISC-V SoC available today.

In which direction is the technology transfer going?

[1] or possibly 24 dual-socket boards, shown at the RISC-V Summit China in August

[2] get your own here https://www.crowdsupply.com/milk-v/milk-v-pioneer

For "coming down the pipeline" they're essentially free.

Today, the c910 is an Apache 2, hardware proven out of order core on GitHub here https://github.com/T-head-Semi/openc910 a little slower than an RPi3's core.

Here is the source code* for the CPU:

https://github.com/T-head-Semi/openc910

* AFAIK they didn't opensource the pre ratification vector extension implementation they ship with the taped out chip.

The source RTL for the roughly Arm A72-equivalent cores used in this were open-sourced several years ago.

https://github.com/T-head-Semi/openc910

The same cores are used in the 64 core SG2042 workstation/server SoC.

It's a shame, because it was the best design from ARM; they're now focusing on Cortex-A7x and Cortex-X, which aren't anywhere as power efficient[0].

Meanwhile, their revised Cortex-A57 has been surpassed in performance/power/area by several RISC-V microarchitectures, such as SiFive's U74[1], used in the VisionFive2 and Star64, or even the open source XuanTie C910[2][3].

0. https://www.youtube.com/watch?v=s0ukXDnWlTY

1. https://www.sifive.com/cores/u74

2. https://xrvm.com/cpu-details?id=4056743610438262784

3. https://github.com/T-head-Semi/openc910