openc910
openc906
openc910 | openc906 | |
---|---|---|
43 | 14 | |
1,128 | 311 | |
1.6% | 8.4% | |
2.6 | 3.4 | |
2 months ago | 2 months ago | |
Verilog | Verilog | |
Apache License 2.0 | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
openc910
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RISC-V must get its messaging right on open standard vs. open source
Not noted here is that the fastest RISC-V general purpose machines you can currently buy use the THead C910 core, which is:
1) Chinese
2) actually Open Source (except the vector unit): https://github.com/T-head-Semi/openc910
The fastest off the shelf RISC-V machine currently is the Milk-V Pioneer using the SG2042 SoC which has 64 C910 OoO cores running at 2.0 GHz, with 64 MB L3 cache and up to 128 GB RAM. The core, SoC, board, and PC are all made in China.
Of course this situation changes very fast. There will be several machines using SiFive's P550 cores in several months -- most from Chinese companies, or at least using Chinese SoC (SiFive's own HiFive Premier P550 board). And then at the end of the year the Milk-V "Oasis" (and others from at least Sipeed) using SiFive's P670 cores, but again in the Chinese SG2380 SoC.
There are a several US startups who started work on RISC-V core in 2021-2022 who will have much faster (Apple M1 class or better) cores, but those won't arrive in machines you can buy until 2025 or 2026.
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US Government reportedly ponders crimping China's use of RISC-V
> I'm pretty sure that SiFive isn't allowed to sell their RISC-V core designs to any Chinese company already.
The JH7110 SoC from the Chinese firm Starfive uses SiFive's U74 core. Eswin, also Chinese uses SiFive's P550 core in their upcoming EIC7700 SoC.
> All Chinese RISC-V core designs have been proprietary designs thus far.
There is the OpenC910 [1] and OpenXiangShan [2].
[1] https://github.com/T-head-Semi/openc910
- Lichee Console 4A β RISC-V mini laptop: Review, benchmarks and early issues
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Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU
Note that the C910 CPU cores used in this chip are in fact open source:
https://github.com/T-head-Semi/openc910
(C920 is just C910 plus RVV draft 0.7.1 vector unit which pretty much no software uses anyway, sadly)
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This CPU is FREE!
The Milk-V Pioneer uses a C910 CPU, which has been open sourced by t-head: https://github.com/T-head-Semi/openc910
- LTT
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China Deploys RISC-V Server in Commercial Cloud
More precisely, a Chinese university assembled a rack containing 48 [1] commercially available SBCs [2], each with a Chinese-designed and made SG2042 SoC with 64 C910 CPU cores. The C910 was designed in China in 2018/19 and open-sourced in October 2021, on Microsoft's github site.
https://github.com/T-head-Semi/openc910
The SG2042 is the most powerful RISC-V SoC available today.
In which direction is the technology transfer going?
[1] or possibly 24 dual-socket boards, shown at the RISC-V Summit China in August
[2] get your own here https://www.crowdsupply.com/milk-v/milk-v-pioneer
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Raspberry Pi receives strategic investment from Arm
For "coming down the pipeline" they're essentially free.
Today, the c910 is an Apache 2, hardware proven out of order core on GitHub here https://github.com/T-head-Semi/openc910 a little slower than an RPi3's core.
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Lichee Pi 4A: Serious RISC-V Desktop Computing [video]
Here is the source code* for the CPU:
https://github.com/T-head-Semi/openc910
* AFAIK they didn't opensource the pre ratification vector extension implementation they ship with the taped out chip.
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Beagleboard BeagleV-Ahead RISC-V brd released
The source RTL for the roughly Arm A72-equivalent cores used in this were open-sourced several years ago.
https://github.com/T-head-Semi/openc910
The same cores are used in the 64 core SG2042 workstation/server SoC.
openc906
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Milk-V Duo: A $9 RISC-V COMPUTER
Datasheet: https://github.com/milkv-duo/hardware
Reading the datasheet, it looks like there is one C906 cpu with 700 Mhz without the the vector extension and one C906 cpu at 1Ghz with rvv 0.7.1. The C906 design has been opensourced and is available here: https://github.com/T-head-Semi/openc906
The C906 supports rv64gc with optimal rvv 0.7.1 with a vlen of 128, but a 256 wide ALU.
They list H.264/H.265 support, but I don't think it's a standardized extension.
But see my other comment about using the pre ratification vector extension:
- New RISC-V SoCs. Are they private and secure, or just more of the same?
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ARM versus RISC-V
Note that the implementations themselves are often not open source, for example a random person won't be able to get the sources of these SiFive cores anywhere. As of a open-source core from a commercial company, the OpenC906 is an open-source implementation provided by T-Head, but the vector unit is not included in the open source version and thus cannot enabled.
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Core2Duo doesnt have backdoor
Still not free hardware, real chads use XuanTie C906 based MangoPi MQ-PRO!
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Google wants RISC-V to be a βtier-1β Android architecture
Try and see if you can find any stolen code here[0] or here[1].
Cheers.
0. https://github.com/T-head-Semi/openc906
1. https://github.com/T-head-Semi/openc910
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RISC-V Pushes into the Mainstream
I wouldn't quite say that's the case. Two of the three full Linux capable RISC-V SoC releases this year are using open source CPU cores. The BL808 and the Allwinner D1 both use T-Head CPU cores that are available on GitHub https://github.com/T-head-Semi/openc906 . The JH7110 in the VisionFive2 and Star 64 does use a closed CPU core however.
- Store access fault when executing AMO instructions in Nezha D1
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Does a truly secure Linux system exist?
For example, let's take the ClockworkPi uConsole. It uses an Allwinner D1 chip as it's main processor which has a seemingly auditable XuanTie C906 which could theoretically be verified if one opened up a few chips.
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Buying RISC-V development board
For an example of what CPU core RTL looks like look no further than: https://github.com/T-head-Semi/openc906
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Packed-SIMD (P) vs Vector (V) extension
For example, for the record, the open source C906 RTL, found here https://github.com/T-head-Semi/openc906 doesn't even have the vector files in there.
What are some alternatives?
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
aosp-riscv - Patches & Script for AOSP to run on Xuantie RISC-V CPU [Moved to: https://github.com/T-head-Semi/riscv-aosp]
XiangShan - Open-source high-performance RISC-V processor
xuantie-yocto - Yocto project for Xuantie RISC-V CPU
riscv-profiles - RISC-V Architecture Profiles
awesome-riscv - π A curated list of awesome RISC-V implementations
riscv-aosp - Patches & Script for AOSP to run on Xuantie RISC-V CPU
seL4 - The seL4 microkernel
linux - Patches include sunxi platform support and various driver fixes
vroom - VRoom! RISC-V CPU