openc906 VS riscv-profiles

Datasheet: https://github.com/milkv-duo/hardware

Reading the datasheet, it looks like there is one C906 cpu with 700 Mhz without the the vector extension and one C906 cpu at 1Ghz with rvv 0.7.1. The C906 design has been opensourced and is available here: https://github.com/T-head-Semi/openc906

The C906 supports rv64gc with optimal rvv 0.7.1 with a vlen of 128, but a 256 wide ALU.

They list H.264/H.265 support, but I don't think it's a standardized extension.

But see my other comment about using the pre ratification vector extension:

Note that the implementations themselves are often not open source, for example a random person won't be able to get the sources of these SiFive cores anywhere. As of a open-source core from a commercial company, the OpenC906 is an open-source implementation provided by T-Head, but the vector unit is not included in the open source version and thus cannot enabled.

Still not free hardware, real chads use XuanTie C906 based MangoPi MQ-PRO!

Try and see if you can find any stolen code here[0] or here[1].

Cheers.

0. https://github.com/T-head-Semi/openc906

1. https://github.com/T-head-Semi/openc910

I wouldn't quite say that's the case. Two of the three full Linux capable RISC-V SoC releases this year are using open source CPU cores. The BL808 and the Allwinner D1 both use T-Head CPU cores that are available on GitHub https://github.com/T-head-Semi/openc906 . The JH7110 in the VisionFive2 and Star 64 does use a closed CPU core however.

For example, let's take the ClockworkPi uConsole. It uses an Allwinner D1 chip as it's main processor which has a seemingly auditable XuanTie C906 which could theoretically be verified if one opened up a few chips.

For an example of what CPU core RTL looks like look no further than: https://github.com/T-head-Semi/openc906

For example, for the record, the open source C906 RTL, found here https://github.com/T-head-Semi/openc906 doesn't even have the vector files in there.

Ssstrict is supposed to address the undefined behaviour problem, or at least it'll make undefined instructions actually trap.

https://github.com/riscv/riscv-profiles/blob/main/rva23-prof...

>there are a lot of incompatible ISA implementations of RISC-V

This is common FUD.

In reality, most chips in the market, including all known application processors, follow the RVA profile[0] spec.

So do Linux distributions.

0. https://github.com/riscv/riscv-profiles/releases

The bit manipulation [0] extension has been ratified for a while now and is part of the RVA22 application extension profile [1].

You can already buy SOCs that support it, e.g. vision five 2 and star64.

Interestingly the risc-v vector has it's own popcount instructions for vector registers/register masks. This is needed, because the scalable architecture doesn't guarantee that a vector mask can fit into a 64 bit register, so vector masks are stored in a single LMUL=1 register. This works really well, because with LMUL=8 and SEW=8 you get 100% utilization of the single LMUL=1 vector register.

Another interesting thing is that the vector crypto extension will likely introduce a element wise popcount instruction.

[0] https://github.com/riscv/riscv-bitmanip/releases/download/1....

[1] https://github.com/riscv/riscv-profiles/blob/main/profiles.a...

That's why we have RISC-V profiles.

Yeah more or less. They now have RISC-V Application Profiles which are basically minimum requirements for "application processors" - essentially devices like phones where you might want to distribute binary apps.

The Profiles spec which includes RVA22 was finally ratified[0] last week.

0. https://github.com/riscv/riscv-profiles/releases/tag/v1.0

Context: RISC-V profiles spec got ratified last week.

Yeah unfortunately there isn't really a great place that lists all the extensions with links and ratification status.

But anyway there is a sort of standard set of extensions that "application processors" (I guess CPUs that want to run precompiled code) should support:

https://github.com/riscv/riscv-profiles/blob/main/profiles.a...

The 22 indicates the year.

Ah, you're right: https://github.com/riscv/riscv-profiles/blob/main/profiles.a...

That's good to see. (Boy, it's really hard to find info about RISC-V profiles on Google. It just seems to ignore all the letters and numbers.)