How to improve the RISC-V specification

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  • sail-riscv

    Sail RISC-V model

  • I've been doing a lot of work with Sail (not SAIL btw) and I'm not sure I agree with the points about it.

    There's already a way to extract functions into asciidoc as the author noted. I've used it. It works well.

    The liquid types do take some getting used to but they aren't actually used in most of the code; mostly for utility function definitions like `zero_extend`. If you look at the definition for simple instructions they can be very readable and practically pseudocode:

    https://github.com/riscv/sail-riscv/blob/0aae5bc7f57df4ebedd...

    A lot of instructions are more complex or course but that's what you get if you want to precisely define them.

    Overall Sail is a really fantastic language and the liquid types really help avoid bugs.

    The biggest actual problems are:

    1. The RISC-V spec is chock full of undefined / implementation defined behaviour. How do you capture that in code, where basically everything is defined. The biggest example is probably WARL fields which can do basically anything. Another example is decomposing misaligned accesses. You can decompose them into any number of atomic memory operations and do them in any order. E.g. Spike decomposes them into single byte accesses. (This problem isn't really unique to Sail tbf).

    2. The RISC-V Sail model doesn't do a good job of letting you configure it currently. E.g. you can't even set the spec version at the moment. This is just an engineering problem though. We're hoping to fix it one day using riscv-config which is a YAML file that's supposed to specify all the configurable behaviour about a RISC-V chip.

    I definitely agree about the often wooly language in the spec though. It doesn't even use RFC-style MUST/SHOULD/MAY terms.

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  • sail

    Sail architecture definition language (by rems-project)

  • Sail is pretty similar to ASL (both current ASL and ASL 1.0) except that (1) it has a more expressive type system, so that bitvector lengths can all be statically checked, (2) it has proper tagged unions and pattern matching, and (3) there's a wide range of open-source tooling available, for execution, specification coverage, generating emulators, integrating with relaxed concurrency models, generating theorem-prover definitions, etc. We've recently updated the Sail README, which spells some of this out: https://github.com/rems-project/sail .

    As Alastair Reid says, one of the main things missing in the current RISC-V specification documents is simply that the associated Sail definitions are not yet interspersed with the prose instruction descriptions. The infrastructure to do that has been available for some time, in the Sail AsciiDoc support by Alasdair Armstrong (https://github.com/Alasdair/asciidoctor-sail/blob/master/doc...) and older LaTeX versions by Prashanth Mundkur and Alasdair (https://github.com/rems-project/riscv-isa-manual/blob/sail/r...).

  • asciidoctor-sail

    Sail Asciidoctor plugin

  • Sail is pretty similar to ASL (both current ASL and ASL 1.0) except that (1) it has a more expressive type system, so that bitvector lengths can all be statically checked, (2) it has proper tagged unions and pattern matching, and (3) there's a wide range of open-source tooling available, for execution, specification coverage, generating emulators, integrating with relaxed concurrency models, generating theorem-prover definitions, etc. We've recently updated the Sail README, which spells some of this out: https://github.com/rems-project/sail .

    As Alastair Reid says, one of the main things missing in the current RISC-V specification documents is simply that the associated Sail definitions are not yet interspersed with the prose instruction descriptions. The infrastructure to do that has been available for some time, in the Sail AsciiDoc support by Alasdair Armstrong (https://github.com/Alasdair/asciidoctor-sail/blob/master/doc...) and older LaTeX versions by Prashanth Mundkur and Alasdair (https://github.com/rems-project/riscv-isa-manual/blob/sail/r...).

  • riscv-isa-manual

    RISC-V Instruction Set Manual (by rems-project)

  • Sail is pretty similar to ASL (both current ASL and ASL 1.0) except that (1) it has a more expressive type system, so that bitvector lengths can all be statically checked, (2) it has proper tagged unions and pattern matching, and (3) there's a wide range of open-source tooling available, for execution, specification coverage, generating emulators, integrating with relaxed concurrency models, generating theorem-prover definitions, etc. We've recently updated the Sail README, which spells some of this out: https://github.com/rems-project/sail .

    As Alastair Reid says, one of the main things missing in the current RISC-V specification documents is simply that the associated Sail definitions are not yet interspersed with the prose instruction descriptions. The infrastructure to do that has been available for some time, in the Sail AsciiDoc support by Alasdair Armstrong (https://github.com/Alasdair/asciidoctor-sail/blob/master/doc...) and older LaTeX versions by Prashanth Mundkur and Alasdair (https://github.com/rems-project/riscv-isa-manual/blob/sail/r...).

  • riscv-profiles

    RISC-V Architecture Profiles

  • Ssstrict is supposed to address the undefined behaviour problem, or at least it'll make undefined instructions actually trap.

    https://github.com/riscv/riscv-profiles/blob/main/rva23-prof...

  • riscv-isa-manual

    RISC-V Instruction Set Manual

  • I encourage you to look at the newest isa manual draft on github: https://github.com/riscv/riscv-isa-manual/releases

    It includes the more recently extensions, and e.g. the bitmanip instructions all have associated pseudo code.

    Here is e.g. the code for cpopw:

        let bitcount = 0;

  • tinyrv

    A tiny RISC-V instruction decoder and instruction set simulator

  • Here is one in less than 200 lines of python: https://github.com/s-holst/tinyrv .

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  • riscv-opcodes

    RISC-V Opcodes

  • It uses machine-readable specs from https://github.com/riscv/riscv-opcodes ; yet I needed to extract immediate bit scrambling from their LaTeX sources :). I wonder if there is an easier way. Anyways, the opcode semantics are hand-coded and it simulates enough to boot linux.

  • herdtools7

    The Herd toolsuite to deal with .cat memory models (version 7.xx)

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