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Random instruction generator for RISC-V processor verification
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RISC-V architecture concurrency model litmus tests
Areas to contribute in RISC-V RTL verification
reddit.com/r/RISCV | 2021-03-06
Doing something leveraging the SAIL model would be valuable, as that's the official formal model: https://github.com/rems-project/sail-riscv
rems-project/sail-riscv is an open source project licensed under GNU General Public License v3.0 or later which is an OSI approved license.