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sail-riscv reviews and mentions
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RISC-V Vector benchmark results
The official formal specification of the Vector Extension has just been merged into the Golden RISC-V model:
https://github.com/riscv/sail-riscv/commit/c90cf2e6eff5fa4ef...
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Cascade: CPU Fuzzing via Intricate Program Generation
the retired instruction counters when written by software.
Funnily enough the Sail model had this bug too! https://github.com/riscv/sail-riscv/issues/256
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Arm’s Cortex A510: Two Kids in a Trench Coat
> loose specification of the RISC-V ISA.
This is being worked on with the Sail model [1]. In order for a RISC-V extension to be ratified it ought to be implemented in Sail. The understanding is also that the RISC-V ISA manual should be built with code snippets from the Sail model (similar to how the Arm Arm is build from ASL definition). The main issue is a lack of people willing and able to write Sail for RISC-V. But that is beginning to change, since RISC-V member companies are increasingly use Sail. As an example, the RISC-V exception type is defined in [2]. Is that precise enough for you?
[1] https://github.com/riscv/sail-riscv
[2] https://github.com/riscv/sail-riscv/blob/master/model/riscv_...
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RISC-V CPU formal specification F# edition
>it allows to formally verify the correctness of a particular ISA
That must be hypothetical. Functionalness of the language doesn't make anything that is written in it automatically subject to formal verification. (mechanized or pen and paper). What kind of correctness properties does it actually allow to formally verify? I understand if it was the F* language, which is a full blown dependently typed proof checker, but with F#, which is defined by the implementation and 300 page English spec, I don't think you can verify anything interesting. As far as I know F# itself doesn't have mechanized formal semantics and its type system could be unsound.
https://github.com/mit-plv/riscv-coq and https://github.com/riscv/sail-riscv (don't know how complete they are) approaches actually allow to formally (mechanically) verify riscv properties.
- 64-bit Arm ∩ 64-bit RISC V
- C++17 RISC-V RV32/64/128 userspace emulator library
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Starting up with RISC-V
I guess you will also use Spike and the Sail model for RISC-V.
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Areas to contribute in RISC-V RTL verification
Doing something leveraging the SAIL model would be valuable, as that's the official formal model: https://github.com/rems-project/sail-riscv
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A note from our sponsor - WorkOS
workos.com | 24 Apr 2024
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riscv/sail-riscv is an open source project licensed under GNU General Public License v3.0 or later which is an OSI approved license.
The primary programming language of sail-riscv is Coq.
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