sail-riscv

Sail RISC-V model (by riscv)

Sail-riscv Alternatives

Similar projects and alternatives to sail-riscv

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better sail-riscv alternative or higher similarity.

sail-riscv reviews and mentions

Posts with mentions or reviews of sail-riscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-11-11.
  • RISC-V Vector benchmark results
    4 projects | news.ycombinator.com | 11 Nov 2023
    The official formal specification of the Vector Extension has just been merged into the Golden RISC-V model:

    https://github.com/riscv/sail-riscv/commit/c90cf2e6eff5fa4ef...

  • Cascade: CPU Fuzzing via Intricate Program Generation
    3 projects | news.ycombinator.com | 23 Oct 2023
    the retired instruction counters when written by software.

    Funnily enough the Sail model had this bug too! https://github.com/riscv/sail-riscv/issues/256

  • Arm’s Cortex A510: Two Kids in a Trench Coat
    1 project | news.ycombinator.com | 2 Oct 2023
    > loose specification of the RISC-V ISA.

    This is being worked on with the Sail model [1]. In order for a RISC-V extension to be ratified it ought to be implemented in Sail. The understanding is also that the RISC-V ISA manual should be built with code snippets from the Sail model (similar to how the Arm Arm is build from ASL definition). The main issue is a lack of people willing and able to write Sail for RISC-V. But that is beginning to change, since RISC-V member companies are increasingly use Sail. As an example, the RISC-V exception type is defined in [2]. Is that precise enough for you?

    [1] https://github.com/riscv/sail-riscv

    [2] https://github.com/riscv/sail-riscv/blob/master/model/riscv_...

  • RISC-V CPU formal specification F# edition
    6 projects | news.ycombinator.com | 28 Jul 2023
    >it allows to formally verify the correctness of a particular ISA

    That must be hypothetical. Functionalness of the language doesn't make anything that is written in it automatically subject to formal verification. (mechanized or pen and paper). What kind of correctness properties does it actually allow to formally verify? I understand if it was the F* language, which is a full blown dependently typed proof checker, but with F#, which is defined by the implementation and 300 page English spec, I don't think you can verify anything interesting. As far as I know F# itself doesn't have mechanized formal semantics and its type system could be unsound.

    https://github.com/mit-plv/riscv-coq and https://github.com/riscv/sail-riscv (don't know how complete they are) approaches actually allow to formally (mechanically) verify riscv properties.

  • 64-bit Arm ∩ 64-bit RISC V
    2 projects | /r/asm | 7 Jun 2023
  • C++17 RISC-V RV32/64/128 userspace emulator library
    5 projects | news.ycombinator.com | 18 Nov 2022
  • Starting up with RISC-V
    3 projects | /r/RISCV | 4 Feb 2022
    I guess you will also use Spike and the Sail model for RISC-V.
  • Areas to contribute in RISC-V RTL verification
    5 projects | /r/RISCV | 6 Mar 2021
    Doing something leveraging the SAIL model would be valuable, as that's the official formal model: https://github.com/rems-project/sail-riscv
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3 days ago

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