riscv-profiles
riscv-platform-specs
riscv-profiles | riscv-platform-specs | |
---|---|---|
21 | 9 | |
87 | 109 | |
- | - | |
8.0 | 0.0 | |
19 days ago | 8 months ago | |
Makefile | Makefile | |
Creative Commons Attribution 4.0 | Creative Commons Attribution 4.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-profiles
-
How to improve the RISC-V specification
Ssstrict is supposed to address the undefined behaviour problem, or at least it'll make undefined instructions actually trap.
https://github.com/riscv/riscv-profiles/blob/main/rva23-prof...
-
Raspberry Pi receives strategic investment from Arm
>there are a lot of incompatible ISA implementations of RISC-V
This is common FUD.
In reality, most chips in the market, including all known application processors, follow the RVA profile[0] spec.
So do Linux distributions.
0. https://github.com/riscv/riscv-profiles/releases
-
You Won’t Believe This One Weird CPU Instruction (2019)
The bit manipulation [0] extension has been ratified for a while now and is part of the RVA22 application extension profile [1].
You can already buy SOCs that support it, e.g. vision five 2 and star64.
Interestingly the risc-v vector has it's own popcount instructions for vector registers/register masks. This is needed, because the scalable architecture doesn't guarantee that a vector mask can fit into a 64 bit register, so vector masks are stored in a single LMUL=1 register. This works really well, because with LMUL=8 and SEW=8 you get 100% utilization of the single LMUL=1 vector register.
Another interesting thing is that the vector crypto extension will likely introduce a element wise popcount instruction.
[0] https://github.com/riscv/riscv-bitmanip/releases/download/1....
[1] https://github.com/riscv/riscv-profiles/blob/main/profiles.a...
-
The legend of "x86 CPUs decode instructions into RISC form internally"
That's why we have RISC-V profiles.
-
Why is std::hardware_destructive_interference_size a compile-time constant instead of a run-time value?
Yeah more or less. They now have RISC-V Application Profiles which are basically minimum requirements for "application processors" - essentially devices like phones where you might want to distribute binary apps.
-
RISC-V Profiles: Defining sets of extensions for coherent ecosystems
The Profiles spec which includes RVA22 was finally ratified[0] last week.
0. https://github.com/riscv/riscv-profiles/releases/tag/v1.0
-
RISC-V Profiles
Context: RISC-V profiles spec got ratified last week.
- Questions about standard extensions
-
RISC-V Business: Testing StarFive's VisionFive 2 SBC
Yeah unfortunately there isn't really a great place that lists all the extensions with links and ratification status.
But anyway there is a sort of standard set of extensions that "application processors" (I guess CPUs that want to run precompiled code) should support:
https://github.com/riscv/riscv-profiles/blob/main/profiles.a...
The 22 indicates the year.
-
TinyEMU – x86 and RISC-V emulator, small and simple while being complete
Ah, you're right: https://github.com/riscv/riscv-profiles/blob/main/profiles.a...
That's good to see. (Boy, it's really hard to find info about RISC-V profiles on Google. It just seems to ignore all the letters and numbers.)
riscv-platform-specs
-
Milk-V Mars: RISC-V credit card size SBC
For the higher end "Application" cores that do e.g. run Linux, there's a platform standardization effort. Refer to OS-A platform[0].
0. https://github.com/riscv/riscv-platform-specs/blob/main/risc...
-
ARM or x86? ISA Doesn’t Matter
>What does matter is standardization. For example a booting process.
Truth.
This is why RISC-V put a lot of effort on this, and put it early.
Relevant specs include but isn't limited to SBI[0], UEFI protocol[1] and the ongoing platform specification[2].
0. https://github.com/riscv-non-isa/riscv-sbi-doc/releases
1. https://github.com/riscv-non-isa/riscv-uefi/releases/tag/1.0...
2. https://github.com/riscv/riscv-platform-specs
- $70 RISC-V Computer from Pine64 Goes on Sale April 4 – OMG Linux
-
Ubuntu on new RISC-V boards: thoughts?
For the record the RISC-V foundation already has a working group developing platform standards. Currently they have OS-A Server for servers, OS-A Embedded for small boards and the M platform for Zephyr/Linux NOMMU size systems. https://github.com/riscv/riscv-platform-specs/blob/main/riscv-platform-spec.pdf
-
IBM PC like extensions for SBI
The SBI console stuff are deprecated with no replacements. And if you checkout https://github.com/riscv/riscv-platform-specs/blob/main/riscv-platform-spec.adoc, OS kernels really are expected to just find a 8250 or 16550 in the device tree, or as mentioned in a few other comments, use UEFI.
-
Addressing Criticism of RISC-V Microprocessors
Platforms: https://github.com/riscv/riscv-platform-specs/blob/main/riscv-platform-spec.adoc
-
SiFive HiFive Unmatched successor in the works
There’s no indication of when the next iteration of the “Un” board will be, but it would be interesting to see if they’re targeting today’s tech, or something that’s around the corner such as the upcoming platform spec https://github.com/riscv/riscv-platform-specs/blob/main/riscv-platform-spec.adoc
-
RISC-V Int. Ratifies 15 New Specs, Opening Up New RISC-V Design Possibilities
If you're building a chip for a server, workstation, cellphone you'll want to adhere to the platform spec.
RVA22[0] is the first one, and among other important things which go a long way to ease cross-vendor software compatibility, it does specify a set of extensions which are required.
[0]: https://github.com/riscv/riscv-platform-specs/blob/main/risc...
-
New RISCV Specification
You’ll find the current RISC-V platform specification here.
What are some alternatives?
xuantie-yocto - Yocto project for Xuantie RISC-V CPU
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
openc906 - OpenXuantie - OpenC906 Core
riscv-crypto - RISC-V cryptography extensions standardisation work.
riscv-bitmanip - Working draft of the proposed RISC-V Bitmanipulation extension
volk - The Vector Optimized Library of Kernels
riscv-uefi-edk2-docs - Documentation and status of UEFI on RISC-V
riscv-isa-manual - RISC-V Instruction Set Manual
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
vroom - VRoom! RISC-V CPU