openc910 VS XiangShan

Not noted here is that the fastest RISC-V general purpose machines you can currently buy use the THead C910 core, which is:

1) Chinese

2) actually Open Source (except the vector unit): https://github.com/T-head-Semi/openc910

The fastest off the shelf RISC-V machine currently is the Milk-V Pioneer using the SG2042 SoC which has 64 C910 OoO cores running at 2.0 GHz, with 64 MB L3 cache and up to 128 GB RAM. The core, SoC, board, and PC are all made in China.

Of course this situation changes very fast. There will be several machines using SiFive's P550 cores in several months -- most from Chinese companies, or at least using Chinese SoC (SiFive's own HiFive Premier P550 board). And then at the end of the year the Milk-V "Oasis" (and others from at least Sipeed) using SiFive's P670 cores, but again in the Chinese SG2380 SoC.

There are a several US startups who started work on RISC-V core in 2021-2022 who will have much faster (Apple M1 class or better) cores, but those won't arrive in machines you can buy until 2025 or 2026.

> I'm pretty sure that SiFive isn't allowed to sell their RISC-V core designs to any Chinese company already.

The JH7110 SoC from the Chinese firm Starfive uses SiFive's U74 core. Eswin, also Chinese uses SiFive's P550 core in their upcoming EIC7700 SoC.

> All Chinese RISC-V core designs have been proprietary designs thus far.

There is the OpenC910 [1] and OpenXiangShan [2].

[1] https://github.com/T-head-Semi/openc910

Note that the C910 CPU cores used in this chip are in fact open source:

https://github.com/T-head-Semi/openc910

(C920 is just C910 plus RVV draft 0.7.1 vector unit which pretty much no software uses anyway, sadly)

The Milk-V Pioneer uses a C910 CPU, which has been open sourced by t-head: https://github.com/T-head-Semi/openc910

More precisely, a Chinese university assembled a rack containing 48 [1] commercially available SBCs [2], each with a Chinese-designed and made SG2042 SoC with 64 C910 CPU cores. The C910 was designed in China in 2018/19 and open-sourced in October 2021, on Microsoft's github site.

https://github.com/T-head-Semi/openc910

The SG2042 is the most powerful RISC-V SoC available today.

In which direction is the technology transfer going?

[1] or possibly 24 dual-socket boards, shown at the RISC-V Summit China in August

[2] get your own here https://www.crowdsupply.com/milk-v/milk-v-pioneer

For "coming down the pipeline" they're essentially free.

Today, the c910 is an Apache 2, hardware proven out of order core on GitHub here https://github.com/T-head-Semi/openc910 a little slower than an RPi3's core.

Here is the source code* for the CPU:

https://github.com/T-head-Semi/openc910

* AFAIK they didn't opensource the pre ratification vector extension implementation they ship with the taped out chip.

The source RTL for the roughly Arm A72-equivalent cores used in this were open-sourced several years ago.

https://github.com/T-head-Semi/openc910

The same cores are used in the 64 core SG2042 workstation/server SoC.

Link to the open-source processor implementation: https://github.com/OpenXiangShan/XiangShan/tree/nanhu

You can download and simulate it on regular hardware.

I ran a few micro benchmarks it XiangShanV2 (Nanhu), the one in the laptop, and XiangShanV3 the next generation of their implementation:

    integer micro benchmark from the XiangShan repo:

Are you calling for the government to pick a winner? The Chinese word for this fierce if at times chaotic competition is "juan". It worked for them in EV and PV. The outcome remains to be seen in chips and commercial space launches. But even their mostly (ex-)students-run open source Xiangshan RiscV project https://github.com/OpenXiangShan/XiangShan shows a remarkable level of sophistication.

> Certainly no RISC-V implementations that are in the hands of customers right now do any fusion and it doesn't seem to hurt their ability to match or exceed the performance of similar Arm cores (A55, A72).

You can play around with OpenXianShan though, they have a few fusion targets: https://github.com/OpenXiangShan/XiangShan/blob/master/src/m...

Most of the targets require the same destination, so it won't be able to fuse current codegen. I suppose there is still some time before compilers need to be ready, but it's not that much.

> Perhaps they will provide compiler patches if required.

I hope so, btw t-head seems to be still be trying to upstream XTheadVector: https://gcc.gnu.org/pipermail/gcc-patches/2024-January/64278...

This is the most advanced open source risc-v implementation I'm awair of: https://github.com/OpenXiangShan/XiangShan

Maybe implement a big feature for a open source design? like vroom or xiangshan.

I did know about XiangShan, but not Aolai. Is it a Linux distribution?

If you are interested in high performance look into vroom , c910 and xianghan, maybe you could adopt one of them.