MRISC32 – An Open 32-Bit RISC/Vector ISA (Suitable for FPGA CPU)

• mrisc32-gnu-toolchain

  2 - -

• XiangShan

  32 4,305 9.3 Scala

  Open-source high-performance RISC-V processor

  

> Certainly no RISC-V implementations that are in the hands of customers right now do any fusion and it doesn't seem to hurt their ability to match or exceed the performance of similar Arm cores (A55, A72).

You can play around with OpenXianShan though, they have a few fusion targets: https://github.com/OpenXiangShan/XiangShan/blob/master/src/m...

Most of the targets require the same destination, so it won't be able to fuse current codegen. I suppose there is still some time before compilers need to be ready, but it's not that much.

> Perhaps they will provide compiler patches if required.

I hope so, btw t-head seems to be still be trying to upstream XTheadVector: https://gcc.gnu.org/pipermail/gcc-patches/2024-January/64278...

• WorkOS

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• llvm-project

  349 25,563 10.0 C++

  The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

  

Looks like llvm recently got some fusion support via -mtune now: https://github.com/llvm/llvm-project/commits/main/llvm/lib/T...

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