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Top 15 C++ risc-v Projects
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WorkOS
The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.
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risc0
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
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Projects
Ted Fried's MicroCore Labs Projects which include microsequencer-based FPGA cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. MCL51, MCL64, MCL65, MCL65+, MCL68, MCL86, MCL86+, MCL86jr, MCLR5, MCLZ8 (by MicroCoreLabs)
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InfluxDB
Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
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riscv-none-elf-gcc-xpack
A binary xPack with the GNU RISC-V Embedded GCC toolchain with support of WCH RISCV CH56x... "WCH-Interrupt-fast" (by hydrausb3)
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cs2410
An out-of-order execution CPU simulator for CS2410 Computer Architecture course final project at the University of Pittsburgh.
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The idea is to write a C++ model that that produces cycle accurate outputs of the branch predictor, core pipeline, queues, memory latency, cache hierarchy, prefetch behaviour, etc. Transistor level accuracy isn't needed as long as the resulting cycle timings are identical or near identical. The improvement in workload runtime compared to a Verilog simulation is precisely because they aren't trying to model every transistor, but just the important parameters which effect performance.
Let's take a simple example: Instead of modeling a 64-bit adder in all its gory transistor level detail, you can just have the model return the correct data after 1 "cycle" or whatever your ALU latency is. As long as that cycle latency is the same as the real hardware, you'll get an accurate performance number.
What's particularly useful about these models is they enable much easier and faster state space exploration to see how a circuit would perform, well before going ahead with the Verilog implementation, which relatively speaking can take circuit designers ages. "How much faster would my CPU be if it had a 20% larger register file" can be answered in a day or two before getting a circuit designer to go try and implement such a thing.
If you want an open source example, take a look at the gem5 project (https://www.gem5.org). It's not quite as sophisticated as the proprietary models used in industry, but it's a used widely in academia and open source hardware design and is a great place to start.
You can actually write zkps in pure Rust, but there's not currently any blockchain integration: https://github.com/risc0/risc0
Project mention: Ask HN: Looking for a project to volunteer on? (November 2023) | news.ycombinator.com | 2023-11-02Seeking: https://github.com/fwsGonzo/libriscv
This is a C++ RISC-V emulator that focuses on isolating a single process, aka userspace emulation. I am currently working mostly on binary translation, and recently I have made a push to move it from experimental state to fully supported. Another experimental feature is embedding libtcc and using that for binary translation. It is fairly fast to compile, and gives decent speedups. The challenge is what to do now that (perhaps) some low hanging fruits have been picked.
most interesting here seems WCH CH32V20* according to their docs https://github.com/wuxx/nanoCH32V305#open-source-toolchain we can use the open source toolchain https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack to build and flash their chips, so no need to use their IDE.
Project mention: Sophie Wilson. She designed the architecture behind your phone’s CPU. She is also a trans woman. | /r/pics | 2023-05-24Here is a CPU simulator that I made during the Spring semester, which implements a subset of the RISC V ISA. :)
It's an open source project, so its not my homework :)https://github.com/Risto97/PeakRDL-halcpp
NOTE:
The open source projects on this list are ordered by number of github stars.
The number of mentions indicates repo mentiontions in the last 12 Months or
since we started tracking (Dec 2020).
C++ risc-v related posts
- MRISC32 – An Open 32-Bit RISC/Vector ISA (Suitable for FPGA CPU)
- Ask HN: Looking for a project to volunteer on? (November 2023)
- Web GUI for the Ripes RISC-V simulator
- Hot Chips 2023: Arm’s Neoverse V2
- Custom Instructions: How do I go from MATCH/MASK to opcode?
- C++ or Rust after having learnt C ?
- Writing a Tiny RISC-V Emulator [video]
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Index
What are some of the best open-source risc-v projects in C++? This list will help you:
| Project | Stars | |
|---|---|---|
| 1 | Ripes | 2,368 |
| 2 | gem5 | 1,412 |
| 3 | risc0 | 1,371 |
| 4 | qtrvsim | 411 |
| 5 | libriscv | 404 |
| 6 | Projects | 349 |
| 7 | bl_iot_sdk | 134 |
| 8 | riscv-none-elf-gcc-xpack | 107 |
| 9 | riscv-perf-model | 98 |
| 10 | gd32vf103inator | 44 |
| 11 | PERCIVAL | 40 |
| 12 | Kite | 13 |
| 13 | riscv-none-elf-gcc-xpack | 11 |
| 14 | cs2410 | 3 |
| 15 | PeakRDL-halcpp | 3 |
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