wd65c02
Cycle accurate FPGA implementation of various 6502 CPU variants (by CompuSAR)
Ben8Bit
Verilog implementation of Ben Eater's 8-bit breadboard computer (by CompuSAR)
wd65c02 | Ben8Bit | |
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8 | 3 | |
27 | 12 | |
- | - | |
0.0 | 4.1 | |
about 2 years ago | over 2 years ago | |
SystemVerilog | Verilog | |
GNU General Public License v3.0 only | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
wd65c02
Posts with mentions or reviews of wd65c02.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-11-15.
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Beginner Verilog Testing Question
I'm implementing a 6502. I wrote a test-bench program in Verilog that takes a mem file for the test program, and another for the test-plan, and verifies the CPU's execution against the test plan. You can check it out. Feel free to steal ideas. You can even use the code itself, so long as you honor the GPL it's under. Here is a link to the actual file inside the project.
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Building Ben's 8-bit CPU in VHDL (to learn a bit about FPGAs). Baby Step 1: Clock Module...
I started such a project in VeriLog once, if you want a reference. I abandoned it before getting to branches, however, in favor of writing a 6502 implementation.
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Stages of prototyping a RISC-V processor on an FPGA?
You can look for ideas at my test bench. The testbench is available here. Don't copy any actual code unless you are willing to abide by the GPL, though. I doubt it will help you in the literal way, anyways, as it is built for testing a CISC CPU, so some adaptations will be required no matter how free you are to use the code. I am hoping it will give you some ideas.
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Debugging a timing loop
I have a design (available here) that has loops in the timing report after implementation. The problem is that I cannot seem to trace the nets I'm seeing in the report to my code, and those I did manage to trace seem to be routed through non-blocking assignments. I'm missing something, but I'm not sure what.
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Help with timing constraints
The project source is here.
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Which is better?
So I went through all the files in the wd65c02/wd65c02.srcs/sources_1/new/ directory, but I can't find the code snippets that you're talking about?
- My Verilog 6502 is progressing
Ben8Bit
Posts with mentions or reviews of Ben8Bit.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-11-15.
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Building Ben's 8-bit CPU in VHDL (to learn a bit about FPGAs). Baby Step 1: Clock Module...
I started such a project in VeriLog once, if you want a reference. I abandoned it before getting to branches, however, in favor of writing a 6502 implementation.
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Why define LUTs and ROMs directly?
My sample CPU is an implementation of Ben Eater's 8-bit machine. You can see it at https://github.com/CompuSAR/Ben8Bit.
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8-Bit computer in Verilog (with source code)
The code is available here.
What are some alternatives?
When comparing wd65c02 and Ben8Bit you can also consider the following projects:
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
verilog-65C02-microcode - 65C02 microprocessor in verilog, small size,reduced cycle count, asynchronous interface
rocket-chip - Rocket Chip Generator