Stages of prototyping a RISC-V processor on an FPGA?

• wd65c02

  8 27 0.0 SystemVerilog

  Cycle accurate FPGA implementation of various 6502 CPU variants

  

You can look for ideas at my test bench. The testbench is available here. Don't copy any actual code unless you are willing to abide by the GPL, though. I doubt it will help you in the literal way, anyways, as it is built for testing a CISC CPU, so some adaptations will be required no matter how free you are to use the code. I am hoping it will give you some ideas.

• rocket-chip

  12 3,017 7.8 Scala

  Rocket Chip Generator

  

My definition of a RISC CPU is one that has a reduced instruction set. In other words, the category of CPU is defined by the size of the instruction set, not in how it is implemented. Consider for example RISC-V CPUs. These are defined by their open instruction set alone, in spite of the fact that many implementations of RISC-V CPUs exist: some pipelined, and some not.

• InfluxDB

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  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• picorv32

  16 2,783 5.2 Verilog

  PicoRV32 - A Size-Optimized RISC-V CPU

  

My definition of a RISC CPU is one that has a reduced instruction set. In other words, the category of CPU is defined by the size of the instruction set, not in how it is implemented. Consider for example RISC-V CPUs. These are defined by their open instruction set alone, in spite of the fact that many implementations of RISC-V CPUs exist: some pipelined, and some not.

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