Rocket Chip Generator (by chipsalliance)

Rocket-chip Alternatives

Similar projects and alternatives to rocket-chip

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better rocket-chip alternative or higher similarity.

rocket-chip reviews and mentions

Posts with mentions or reviews of rocket-chip. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-03-08.
  • Recommendations for RISC-V on FPGA
    7 projects | /r/FPGA | 8 Mar 2023
    Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?
  • RISC-V Pushes into the Mainstream
    5 projects | | 23 Dec 2022
    You could do a trial build of an in-order Rocket RISC-V core [1] to see how much space it takes up.


  • Can anyone explain simply how OpenSource the RISC-V actually is?
    2 projects | /r/RISCV | 8 May 2022
  • Stages of prototyping a RISC-V processor on an FPGA?
    3 projects | /r/FPGA | 21 Oct 2021
    My definition of a RISC CPU is one that has a reduced instruction set. In other words, the category of CPU is defined by the size of the instruction set, not in how it is implemented. Consider for example RISC-V CPUs. These are defined by their open instruction set alone, in spite of the fact that many implementations of RISC-V CPUs exist: some pipelined, and some not.
  • How are modern processors and their architecture designed?
    4 projects | /r/ECE | 28 Sep 2021
    More complex CPUs are typically completely out of scope for hand coding, therefore you can implement generators like:
  • Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
    4 projects | /r/hardware | 8 Sep 2021
    We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores:
  • Project ideas for RISC-V?
    2 projects | /r/RISCV | 6 Jun 2021
    This would allow you to experiment with your own chip or something like [the RocketChip generator](
  • Question: Does the 32bit version of Rocket still supports FPU
    2 projects | /r/RISCV | 14 May 2021
    2 projects | /r/RISCV | 14 May 2021
    You should start tracing through the code to see what that requirement means. Grep through the github repo for things like "rowBits", which brings up this issue ( which may be relevant to your interests.
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