Rocket-chip Alternatives

rocket-chip reviews and mentions

• Recommendations for RISC-V on FPGA
  7 projects | /r/FPGA | 8 Mar 2023

  Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?

• RISC-V Pushes into the Mainstream
  5 projects | news.ycombinator.com | 23 Dec 2022

  You could do a trial build of an in-order Rocket RISC-V core [1] to see how much space it takes up.

  [1] https://github.com/chipsalliance/rocket-chip

• Can anyone explain simply how OpenSource the RISC-V actually is?
  2 projects | /r/RISCV | 8 May 2022
• Stages of prototyping a RISC-V processor on an FPGA?
  3 projects | /r/FPGA | 21 Oct 2021

  My definition of a RISC CPU is one that has a reduced instruction set. In other words, the category of CPU is defined by the size of the instruction set, not in how it is implemented. Consider for example RISC-V CPUs. These are defined by their open instruction set alone, in spite of the fact that many implementations of RISC-V CPUs exist: some pipelined, and some not.

• FPGA for RISC-V Processor
  1 project | /r/FPGA | 1 Oct 2021
• How are modern processors and their architecture designed?
  4 projects | /r/ECE | 28 Sep 2021

  More complex CPUs are typically completely out of scope for hand coding, therefore you can implement generators like: https://github.com/chipsalliance/rocket-chip

• Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
  4 projects | /r/hardware | 8 Sep 2021

  We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip

• Project ideas for RISC-V?
  2 projects | /r/RISCV | 6 Jun 2021

  This would allow you to experiment with your own chip or something like [the RocketChip generator](https://github.com/chipsalliance/rocket-chip).

• Question: Does the 32bit version of Rocket still supports FPU
  2 projects | /r/RISCV | 14 May 2021

  https://github.com/chipsalliance/rocket-chip/blob/c7da610430f51b02ebda37f3d444674dc8f2adbf/src/main/scala/system/Configs.scala#L28

• The First Affordable RISC-V Computer Designed to Run Linux
  1 project | /r/linux | 13 Jan 2021

  I don't know about the u74 specifically, but sifive does seem to invest in a open source risc-v core called rocket-chip.

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