Scala Riscv

Open-source Scala projects categorized as Riscv

Top 5 Scala Riscv Projects

  • rocket-chip

    Rocket Chip Generator

  • riscv-boom

    SonicBOOM: The Berkeley Out-of-Order Machine

  • Project mention: Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU | news.ycombinator.com | 2023-12-10
  • InfluxDB

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  • chipyard

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

  • Project mention: Chisel: A Modern Hardware Design Language | news.ycombinator.com | 2023-12-27

    It's probably true that Chisel isn't right for industry -- Google tried it too for the TPU project and eventually went back to Verilog. That said, I think it's main win is that it is great from a research / open-source perspective.

    Taking advantage of the functional nature of Chisel enables a set of generators called Chipyard [0] for things like cores, networking peripherals, neural network accelerators, etc. If you're focusing on exploring the design space of one particular accelerator and don't care too much about the rest of the chip, you can get a customized version of the RTL for the rest of your chip with ease. All the research projects in the lab benefit from code changes to the generators.

    Chisel even enables undergraduate students (like me!) to tape out a chip on a modern-ish process node in just a semester, letting Chisel significantly reduce the amount of RTL we have to write. Most of the remaining time is spent working on the actual physical design process.

    [0]: https://github.com/ucb-bar/chipyard

    [1]: https://classes.berkeley.edu/content/2023-Spring-ELENG-194-0...

  • riscv-mini

    Simple RISC-V 3-stage Pipeline in Chisel

  • SaxonSoc

    SoC based on VexRiscv and ICE40 UP5K

  • SaaSHub

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Scala Riscv related posts

  • In your opinion, what is the most advanced open source softcore processor?

    2 projects | /r/FPGA | 28 May 2023
  • PyXHDL - Python Frontend For VHDL And Verilog

    2 projects | /r/FPGA | 1 May 2023
  • Semidynamics Unveils First Customizable RISC-V Cores for End Users

    1 project | /r/RISCV | 21 Apr 2023
  • TechTechPotato (Dr Ian Cutress): "Building High-Performance RISC-V Cores for Everything"

    2 projects | /r/hardware | 12 Apr 2023
  • Can anyone explain simply how OpenSource the RISC-V actually is?

    2 projects | /r/RISCV | 8 May 2022
  • Stages of prototyping a RISC-V processor on an FPGA?

    3 projects | /r/FPGA | 21 Oct 2021
  • FPGA for RISC-V Processor

    1 project | /r/FPGA | 1 Oct 2021
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    www.influxdata.com | 4 May 2024
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Index

What are some of the best open-source Riscv projects in Scala? This list will help you:

Project Stars
1 rocket-chip 3,017
2 riscv-boom 1,595
3 chipyard 1,432
4 riscv-mini 498
5 SaxonSoc 141

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