Riscv-boom Alternatives

Similar projects and alternatives to riscv-boom

openc910

43 1,174 2.6 Verilog riscv-boom VS openc910

OpenXuantie - OpenC910 Core
SaaSHub

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riscv-gnu-toolchain

37 3,582 8.5 C riscv-boom VS riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC
rocket-chip

12 3,280 8.8 Scala riscv-boom VS rocket-chip

Rocket Chip Generator
rsd

12 1,008 6.4 SystemVerilog riscv-boom VS rsd

RSD: RISC-V Out-of-Order Superscalar Processor
sandsifter

17 4,911 0.0 Python riscv-boom VS sandsifter

The x86 processor fuzzer
picorv32

17 3,170 5.4 Verilog riscv-boom VS picorv32

PicoRV32 - A Size-Optimized RISC-V CPU
vroom

17 481 2.3 Verilog riscv-boom VS vroom

VRoom! RISC-V CPU (by MoonbaseOtago)
Cores-VeeR-EH1

8 822 0.0 SystemVerilog riscv-boom VS Cores-VeeR-EH1

VeeR EH1 core
sail-riscv

9 467 9.2 Coq riscv-boom VS sail-riscv

Sail RISC-V model
XiangShan

34 4,922 9.9 Scala riscv-boom VS XiangShan

Open-source high-performance RISC-V processor
riscv-mini

1 531 3.4 Scala riscv-boom VS riscv-mini

Discontinued Simple RISC-V 3-stage Pipeline in Chisel
Cores-VeeR-EL2

1 250 9.5 SystemVerilog riscv-boom VS Cores-VeeR-EL2

VeeR EL2 Core
vivado-risc-v

6 862 7.2 Tcl riscv-boom VS vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
neorv32-setups

5 64 8.9 VHDL riscv-boom VS neorv32-setups

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
riscv-cores-list

4 564 1.8 riscv-boom VS riscv-cores-list

Discontinued RISC-V Cores, SoC platforms and SoCs
pyxhdl

2 19 6.0 VHDL riscv-boom VS pyxhdl

Python Frontend For VHDL And Verilog
chipyard

5 1,675 9.7 Scala riscv-boom VS chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
SaxonSoc

1 150 5.0 Scala riscv-boom VS SaxonSoc

SoC based on VexRiscv and ICE40 UP5K
ORCA-risc-v

1 15 10.0 VHDL riscv-boom VS ORCA-risc-v

RISC-V by VectorBlox

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better riscv-boom alternative or higher similarity.

Suggest an alternative to riscv-boom

riscv-boom discussion

riscv-boom reviews and mentions

Posts with mentions or reviews of riscv-boom. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-12-10.

Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU
3 projects | news.ycombinator.com | 10 Dec 2023
Cascade: CPU Fuzzing via Intricate Program Generation
3 projects | news.ycombinator.com | 23 Oct 2023

Looks like from Appendix D that only 2 bugs were found in BOOM:
> 1. Inaccurate instruction count when minstret is written by software
I don't know what that means, but having minstret written by software was definitely not something I ever tested. In general, perf counters are likely to be undertested.
> 2. Static rounding is ignored for fdiv.s and fsqrt.s
A mistake was made in only listening to the dynamic rounding mode for the fdiv/sqrt unit. This is one of those bugs that is trivially found if you test for it, but it turns out that no benchmarking ever cared about this and from all of the fuzzers I used when I worked on BOOM, NONE of them hit it (including commercial ones...). Ooops.
Fixed here: https://github.com/riscv-boom/riscv-boom/pull/629/files
In your opinion, what is the most advanced open source softcore processor?
2 projects | /r/FPGA | 28 May 2023

The two most micro architecturally advanced cores that I know of are BOOM, an out of order RV64GC core with all the features you expect plus sort of weird fancy things like short forward branch predication, and VROOM, another out of order RV64GC core with things like uop fusion and a trace cache.
PyXHDL - Python Frontend For VHDL And Verilog
2 projects | /r/FPGA | 1 May 2023

it is used in the Berkley Out-of-Order RISC-V processor: https://github.com/riscv-boom/riscv-boom
Semidynamics Unveils First Customizable RISC-V Cores for End Users
1 project | /r/RISCV | 21 Apr 2023
TechTechPotato (Dr Ian Cutress): "Building High-Performance RISC-V Cores for Everything"
2 projects | /r/hardware | 12 Apr 2023
Open-source RISC-V CPU projects for contribution
8 projects | /r/RISCV | 28 Jan 2023

SonicBOOM: https://github.com/riscv-boom/riscv-boom
The Surprising Subtleties of Zeroing a Register
3 projects | news.ycombinator.com | 4 Nov 2021

Some cores are open source and you can see for yourself.
Rename logic from BOOM, a RISC-V core written in a DSL embedded in Scala:
https://github.com/riscv-boom/riscv-boom/blob/1ef2bc6f6c98e5...
From RSD, a core designed for FPGAs written in SystemVerilog:
https://github.com/rsd-devel/rsd/blob/master/Processor/Src/R...
And then there's the recently open-sourced XuanTie C910, which contains this Verilog… which is completely unreadable. Seems like it was produced by some kind of code generator that they didn't open-source?
https://github.com/T-head-Semi/openc910/blob/d4a3b947ec9bb8f...
Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
4 projects | /r/hardware | 8 Sep 2021

We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip
Fence instruction implementation in BOOM
1 project | /r/RISCV | 18 Mar 2021

If you look at the decoder (https://github.com/riscv-boom/riscv-boom/blob/master/src/main/scala/exu/decode.scala), you can see that the fence instructions are also marked as "unique" instructions. Only one "unique" instruction is allowed in the pipeline at a time.
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www.saashub.com | 7 Dec 2024

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riscv-boom/riscv-boom is an open source project licensed under BSD 3-clause "New" or "Revised" License which is an OSI approved license.

The primary programming language of riscv-boom is Scala.

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