chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more (by ucb-bar)
Add to my DEV experience rocket-chip chip-generator Chisel Riscv Rtl soc Peripherals chipyard risc-v Boom firesim hwacha accelerators Rocket out-of-order Superscalar
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chipyard.readthedocs.io
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NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better chipyard alternative or higher similarity.
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chipyard reviews and mentions

Posts with mentions or reviews of chipyard. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-12-27.
  • Chisel: A Modern Hardware Design Language
    6 projects | news.ycombinator.com | 27 Dec 2023
    It's probably true that Chisel isn't right for industry -- Google tried it too for the TPU project and eventually went back to Verilog. That said, I think it's main win is that it is great from a research / open-source perspective.

    Taking advantage of the functional nature of Chisel enables a set of generators called Chipyard [0] for things like cores, networking peripherals, neural network accelerators, etc. If you're focusing on exploring the design space of one particular accelerator and don't care too much about the rest of the chip, you can get a customized version of the RTL for the rest of your chip with ease. All the research projects in the lab benefit from code changes to the generators.

    Chisel even enables undergraduate students (like me!) to tape out a chip on a modern-ish process node in just a semester, letting Chisel significantly reduce the amount of RTL we have to write. Most of the remaining time is spent working on the actual physical design process.

    [0]: https://github.com/ucb-bar/chipyard

    [1]: https://classes.berkeley.edu/content/2023-Spring-ELENG-194-0...

  • A repository that tracks upstream but allows separate tracking.
    1 project | /r/git | 3 Apr 2023
    The repo in question is chipyard: https://github.com/ucb-bar/chipyard
  • Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system
    7 projects | news.ycombinator.com | 3 Mar 2023
    Many companies do just write entire modern SoCs in straight Verilog (maybe with some autogenerated Verilog hacked in there) with no other major organization tools aside from the typical project management stuff. The load-store unit of a modern CPU alone easily exceeds 10k lines of Verilog. It's a similar thing as people who work with kernels—after all, the page table management code in a modern operating system like Linux is absolutely monstrous but still people are able to understand it well enough to be able to make the changes they need and get out.

    If you are interested in other languages which hope to make this sort of stuff easier, I'd recommend taking a look at design productivity languages like Chisel and it's associated Chipyard [1], SpinalHDL [2], and Bluespec [3]. Each of these are meant to make defining extremely complex hardware more manageable for humans and there's a lot of interesting work going on right now with each of them.

    [1] https://github.com/ucb-bar/chipyard

    [2] https://github.com/SpinalHDL/SpinalHDL

    [3] https://github.com/B-Lang-org/bsc

  • Chipyard: An Open Source RISC-V SoC Design Framework
    1 project | news.ycombinator.com | 15 Dec 2021
  • How to use a RISC V core for other purposes?
    2 projects | /r/RISCV | 8 Jun 2021
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    www.influxdata.com | 10 May 2024
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Stats

Basic chipyard repo stats
5
1,436
9.7
2 days ago

ucb-bar/chipyard is an open source project licensed under BSD 3-clause "New" or "Revised" License which is an OSI approved license.

The primary programming language of chipyard is Scala.

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