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Stages of prototyping a RISC-V processor on an FPGA?
3 projects | reddit.com/r/FPGA | 21 Oct 2021
My definition of a RISC CPU is one that has a reduced instruction set. In other words, the category of CPU is defined by the size of the instruction set, not in how it is implemented. Consider for example RISC-V CPUs. These are defined by their open instruction set alone, in spite of the fact that many implementations of RISC-V CPUs exist: some pipelined, and some not.
FPGA for RISC-V Processor
1 project | reddit.com/r/FPGA | 1 Oct 2021
How are modern processors and their architecture designed?
4 projects | reddit.com/r/ECE | 28 Sep 2021
More complex CPUs are typically completely out of scope for hand coding, therefore you can implement generators like: https://github.com/chipsalliance/rocket-chip
Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
4 projects | reddit.com/r/hardware | 8 Sep 2021
We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip
Project ideas for RISC-V?
2 projects | reddit.com/r/RISCV | 6 Jun 2021
This would allow you to experiment with your own chip or something like [the RocketChip generator](https://github.com/chipsalliance/rocket-chip).
Question: Does the 32bit version of Rocket still supports FPU
2 projects | reddit.com/r/RISCV | 14 May 2021
https://github.com/chipsalliance/rocket-chip/blob/c7da610430f51b02ebda37f3d444674dc8f2adbf/src/main/scala/system/Configs.scala#L282 projects | reddit.com/r/RISCV | 14 May 2021
You should start tracing through the code to see what that requirement means. Grep through the github repo for things like "rowBits", which brings up this issue (https://github.com/chipsalliance/rocket-chip/issues/1352) which may be relevant to your interests.
The First Affordable RISC-V Computer Designed to Run Linux
1 project | reddit.com/r/linux | 13 Jan 2021
I don't know about the u74 specifically, but sifive does seem to invest in a open source risc-v core called rocket-chip.
Is there an open source application from which to design/build a risc-v ISA processor?
1 project | reddit.com/r/openhardware | 31 Dec 2020
What exactly do you mean? there are various open source tools for hardware design (eda tools), e.g. yosys (used for synthesis), I am not an expert but i don't think they have to be RISC-V specific, the closes thing i can think of that can be RISC-V specific is maybe rocket chip.
What are some alternatives?
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
neorv32 - :desktop_computer: A size-optimized, customizable MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
nuclei-sdk - Nuclei RISC-V Software Development Kit
Cores-SweRV - SweRV EH1 core