bsc

Bluespec Compiler (BSC) (by B-Lang-org)

Bsc Alternatives

Similar projects and alternatives to bsc

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better bsc alternative or higher similarity.

bsc reviews and mentions

Posts with mentions or reviews of bsc. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-03-03.
  • Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system
    7 projects | news.ycombinator.com | 3 Mar 2023
    Many companies do just write entire modern SoCs in straight Verilog (maybe with some autogenerated Verilog hacked in there) with no other major organization tools aside from the typical project management stuff. The load-store unit of a modern CPU alone easily exceeds 10k lines of Verilog. It's a similar thing as people who work with kernels—after all, the page table management code in a modern operating system like Linux is absolutely monstrous but still people are able to understand it well enough to be able to make the changes they need and get out.

    If you are interested in other languages which hope to make this sort of stuff easier, I'd recommend taking a look at design productivity languages like Chisel and it's associated Chipyard [1], SpinalHDL [2], and Bluespec [3]. Each of these are meant to make defining extremely complex hardware more manageable for humans and there's a lot of interesting work going on right now with each of them.

    [1] https://github.com/ucb-bar/chipyard

    [2] https://github.com/SpinalHDL/SpinalHDL

    [3] https://github.com/B-Lang-org/bsc

  • Learning VDHL after knowing Verilog
    2 projects | /r/FPGA | 14 Jan 2023
    What are your thoughts on other HDLs like Chisel or BlueSpec when it comes to better type checking?
  • Is “x' = f(x)” a programming paradigm?
    2 projects | /r/AskProgramming | 9 Nov 2022
    In a previous project we used Haskell that compiled down to Verilog to design hardware. Think along the lines of BlueSpec or Clash. Haskell would force you to spell out the new state as a function of the old state of the system. This would let us do gate-level simulations of the hardware we designed. Coupled with Haskell's penchant for using primes to mean "the new value of", stuff like x' = f x was very common.
  • I'm starting a project to make a Rust-like hardware description language and I need your opinions.
    5 projects | /r/rust | 21 Aug 2022
    You should look at Bluespec, they are doing some interesting stuff.
  • Verilog Is Weird
    4 projects | news.ycombinator.com | 23 Mar 2022
  • Bluespec hardware design language and simulation tools
    1 project | news.ycombinator.com | 1 Feb 2022
  • MyHDL: Using Python as a hardware description and verification language
    3 projects | news.ycombinator.com | 25 Nov 2021
    And I've been involved in a project that's making heavy use of Bluespec: https://github.com/B-Lang-org/bsc/

    Same problem though - you have to transpile it down to Verilog to use it in anything beyond a simulation.

  • FPGA dev board that's cheap, simple and supported by OSS toolchain
    8 projects | news.ycombinator.com | 10 Jan 2021
    FPGA Thread: Bluespec SystemVerilog is now completely open source, very nice HDL although quite opinionated.

    https://github.com/B-Lang-org/bsc

    it's Haskell underneath (https://xkcd.com/356/)

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    www.influxdata.com | 24 Apr 2024
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Stats

Basic bsc repo stats
8
879
8.4
15 days ago

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