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Show HN: A Technolgy-Agnostic Physical Unclonable Function (PUF) for Any FPGA
2 projects | news.ycombinator.com | 16 Nov 2021
(the "platform-agnostic" concept/technique was taken from the NEPORV32 TRNG -> https://github.com/stnolting/neorv32)
A few bits of the raw fingerprint from the module are quite noisy, so a software post-processing is required. I have implemented a simple "averaging" mechanism here. Error correction codes might be much better - but I am still fighting with the theory behind them ;)
I have tested the design on several FPGAs with promising results (see GitHub page). However, I still need to do more long-time testing to ensure stability of the fingerprint.
Feedback is highly appreciated!
FPGA to drive parallel LED strips.
2 projects | reddit.com/r/FPGA | 14 Nov 2021
There is a WS2812 (Neopixel) driver peripheral for 32-bit RGBW and 24-bit RGB LEDs in the NEORV32 RISC-V Processor. Maybe you could re-purpose that. It supports programmable timing parameters so you could also use other serial LEDs.
Beginner FPGA that uses Vivado?
1 project | reddit.com/r/FPGA | 13 Nov 2021
Example project including Nexys-a7: https://github.com/stnolting/neorv32/tree/master/setups
Is there any documentation relates to the riscv-gnu-toolchain ?
4 projects | reddit.com/r/RISCV | 2 Nov 2021
In most cases the start-up code (called crt0) is responsible of doing all the required (hardware) initialization before the C-runtime can take over (setting up the stack pointer, initializing hardware, preparing certain memory sections and so on). Here is an example of one exemplary crt0 start-up code: https://github.com/stnolting/neorv32/blob/master/sw/common/crt0.S4 projects | reddit.com/r/RISCV | 2 Nov 2021
You can also have a look at the NEORV32 RISC-V core's application makefile and especially it's documentation:
The NEORV32 RISC-V Processor: Datasheet
1 project | news.ycombinator.com | 26 Oct 2021
Playing with RISC-V microarchitecture
3 projects | reddit.com/r/RISCV | 25 Oct 2021
The project comes with a fully featured data sheet (https://stnolting.github.io/neorv32/), user guide (https://stnolting.github.io/neorv32/ug/) and software documentation (https://stnolting.github.io/neorv32/sw/files.html).3 projects | reddit.com/r/RISCV | 25 Oct 2021
This is a RISC-V CPU plus SoC in plain VHDL: https://github.com/stnolting/neorv32
Do you filter/synchronize inout? Tri state bus for example.
1 project | reddit.com/r/FPGA | 21 Oct 2021
For example, we are doing that for an I²C module (https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_twi.vhd) and it works without problems.
Open-Source RISC-V SoC for *Any* FPGA
1 project | news.ycombinator.com | 20 Oct 2021
What are some alternatives?
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
picoMIPS - picoMIPS processor doing affine transformation
fpga-zynq - Support for Rocket Chip on Zynq FPGAs
nuclei-sdk - Nuclei RISC-V Software Development Kit
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
riscv_verilator_model - RISCV model for Verilator/FPGA targets
wb2axip - Bus bridges and other odds and ends
pico-png - PNG encoder, implemented in VHDL
autofpga - A utility for Composing FPGA designs from Peripherals
linux-on-litex-rocket - Run 64-bit Linux on LiteX + RocketChip