Scala based HDL (by SpinalHDL)

SpinalHDL Alternatives

Similar projects and alternatives to SpinalHDL

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better SpinalHDL alternative or higher similarity.

SpinalHDL reviews and mentions

Posts with mentions or reviews of SpinalHDL. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-03-03.
  • Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system
    7 projects | news.ycombinator.com | 3 Mar 2023
    Many companies do just write entire modern SoCs in straight Verilog (maybe with some autogenerated Verilog hacked in there) with no other major organization tools aside from the typical project management stuff. The load-store unit of a modern CPU alone easily exceeds 10k lines of Verilog. It's a similar thing as people who work with kernels—after all, the page table management code in a modern operating system like Linux is absolutely monstrous but still people are able to understand it well enough to be able to make the changes they need and get out.

    If you are interested in other languages which hope to make this sort of stuff easier, I'd recommend taking a look at design productivity languages like Chisel and it's associated Chipyard [1], SpinalHDL [2], and Bluespec [3]. Each of these are meant to make defining extremely complex hardware more manageable for humans and there's a lot of interesting work going on right now with each of them.

    [1] https://github.com/ucb-bar/chipyard

    [2] https://github.com/SpinalHDL/SpinalHDL

    [3] https://github.com/B-Lang-org/bsc

  • Simple skid buffer implementation
    3 projects | /r/FPGA | 10 Jan 2023
    I have just found that SpinalHDL also implemented two halves of the fully registered buffer in Stream.scala.
  • Why are there only 3 languages for FPGA development?
    5 projects | /r/FPGA | 1 Dec 2022
    Don’t forget SpinalHDL that was forked off of Chisel 2 I believe. These DSLs really leveraged the software features of Scala to help build generalised/modular systems. And are generally a quality of life improvement in the language features available.
  • Share some github FPGA projects (bonus if they include C++, Python, or other files)
    15 projects | /r/FPGA | 14 Sep 2021
    A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)
  • Suggest advance project ideas
    3 projects | /r/FPGA | 3 Sep 2021
    You could try to implement a PCIe root complex for FOSS SoCs, connecting to e.g. Wishbone as the main bus. There's already some DDR3 controller (or this one) and USB Host controller out there, and even device-side PCIe, but no FOSS host-side PCIe that I know of. Probably quite a difficult job though, even sticking to the lower-speed PCIe 1.
  • Chisel/Firrtl Hardware Compiler Framework
    8 projects | news.ycombinator.com | 5 Jul 2021
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    www.influxdata.com | 9 Dec 2023
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