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Scala Verilog Projects
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Project mention: Spade – A work in progress HDL that doesn't make you want to pull your hair out | news.ycombinator.com | 2025-03-25
How does this compare and contrast to other attempts at succeeding Verilog and VHDL, such as Chisel¹?
1: https://www.chisel-lang.org/
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InfluxDB
InfluxDB – Built for High-Performance Time Series Workloads. InfluxDB 3 OSS is now GA. Transform, enrich, and act on time series data directly in the database. Automate critical tasks and eliminate the need to move data externally. Download now.
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Project mention: A FPGA friendly 32 bit RISC-V CPU implementation | news.ycombinator.com | 2025-01-22
Thank you for the correction! My original comment is too old to correct. It’s so frequently described as one (for example in https://github.com/SpinalHDL/SpinalHDL/issues/202#issuecomme... ) that I assumed they shared a history.
NOTE:
The open source projects on this list are ordered by number of github stars.
The number of mentions indicates repo mentiontions in the last 12 Months or
since we started tracking (Dec 2020).
Scala Verilog discussion
Scala Verilog related posts
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A FPGA friendly 32 bit RISC-V CPU implementation
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1800-2023 – IEEE Standard for SystemVerilog
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SpinalHDL – A high level hardware description language based on Scala
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FPGA Interchange format to enable interoperable FPGA tooling
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Chisel/Firrtl Hardware Compiler Framework
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A note from our sponsor - InfluxDB
www.influxdata.com | 17 May 2025
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