FPGA Interchange format to enable interoperable FPGA tooling

• netlistsvg

  4 585 3.1 JavaScript

  draws an SVG schematic from a JSON netlist

Soon: there are 15 different formats for passing netlists around.

I have very little hope that any netlist format that comes from Yosys. Not only has it changed a couple times in the last years, but the latest iteration is some JSON-based monstrosity that has to be by far the most inconvenient netlist format ever created (see https://github.com/nturley/netlistsvg/blob/master/test/digit... ) .

• python-fpga-interchange

  1 39 0.0 Python

  Python interface to FPGA interchange format

  

Or BLIF or EBLIF (already used by the verilog-to-routing flow). But no, let's invent yet another netlist format.

The fact that all of these existing formats are all named "xxx logic interchange format" should give you an idea what will happen to this new "interchange format".

From what I gather ( https://github.com/SymbiFlow/python-fpga-interchange/blob/ma... ) , the new format is basically the existing Yosys/nextpnr JSON format except dumped as a Cap'n Proto binary file.

I am absolutely not impressed.

I guess the meat here is on the universal device resources format, but this is not cool anyway.

• WorkOS

  workos.com sponsored

  The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

  

• ideas

  2 86 0.0

  Random ideas and interesting ideas for things we hope to eventually do. (by f4pga)

  

• f4pga-arch-defs

  19 247 7.7 Jupyter Notebook

  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

  

• chisel

  25 3,708 9.7 Scala

  Chisel: A Modern Hardware Design Language (by chipsalliance)

  

• firrtl

  4 694 0.0 Scala

  Flexible Intermediate Representation for RTL

  

Did any project other than Chisel make use of FIRRTL? https://github.com/chipsalliance/firrtl

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