Scala Rtl

Open-source Scala projects categorized as Rtl

Top 6 Scala Rtl Projects

  • chisel

    Chisel: A Modern Hardware Design Language (by chipsalliance)

  • Project mention: Calyx: Intermediate Language for Hardware Accelerators | news.ycombinator.com | 2024-02-26

    My first instinct was to ask "Does this play well with CIRCT?" And thankfully they answer that right away in the README.

    I'm personally of the opinion that there is a LOT of room for improvement in the hardware design tooling space, but a combination of market consolidation, huge pressure to meet deadlines, and an existing functional pipeline of Verilog/VHDL talent is preventing changes.

    That's not to say "Verilog/VHDL are bad", because clearly they've been good enough to support nearly all of the wonderful designs powering today's devices. But it is to say, "the startup scene for hardware will continue to look anemic compared to the SaaS scene until someone gives me all of the niceties I have for building SaaS tools in software."

    A huge amount of ideas (and entire designs) start off as software sims, which enables kernel/compiler engineers to start building out support for new hardware before it's manufactured.

    There is some interesting work going on at SiFive building hardware with Chisel[1], as well as some interesting work lead by a professor at William and Mary to improve simulations[2].

    1: https://www.chisel-lang.org

    2: https://github.com/sarchlab/akita

  • rocket-chip

    Rocket Chip Generator

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

    InfluxDB logo
  • riscv-boom

    SonicBOOM: The Berkeley Out-of-Order Machine

  • Project mention: Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU | news.ycombinator.com | 2023-12-10
  • SpinalHDL

    Scala based HDL

  • Project mention: 1800-2023 – IEEE Standard for SystemVerilog | news.ycombinator.com | 2024-04-17

    I'd love to see textual preprocessors kinda banned. Or at least done upstream and outside of the language. You can't both be and also have a textual preprocessor defined internally. It doesn't work.

    I really like what Zig and C++ are doing with `const`.

    https://ikrima.dev/dev-notes/zig/zig-metaprogramming/

    Have you looked at Spinal?

    https://github.com/SpinalHDL/SpinalHDL

    https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html

  • riscv-mini

    Simple RISC-V 3-stage Pipeline in Chisel

  • SaxonSoc

    SoC based on VexRiscv and ICE40 UP5K

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2024-04-17.

Scala Rtl related posts

Index

What are some of the best open-source Rtl projects in Scala? This list will help you:

Project Stars
1 chisel 3,696
2 rocket-chip 3,002
3 riscv-boom 1,584
4 SpinalHDL 1,506
5 riscv-mini 491
6 SaxonSoc 141

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