Chisel/Firrtl Hardware Compiler Framework

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  • chisel

    Chisel: A Modern Hardware Design Language (by chipsalliance)

  • circt

    Circuit IR Compilers and Tools

    Did you see the work being done on CIRCT? https://github.com/llvm/circt

    I remember one of the reasons you did not want to use firrtl was that its compiler is implemented in Scala and thus hard to integrate into other projexts. CIRCT will solve that problem by providing a firrtl compiler implemented in C++. Other languages like Verilog/VHDL and new high level languages for HLS-like designs are also on the todo list.

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  • chiselverify

    A dynamic verification library for Chisel.

    Chisel is not HLS. It is a Scala library that lets you generate circuits on an RTL abstraction level. That means that you explicitly define every state element like registers and memories. But you can generate N registers inside a loop (or a map/foreach) instead of only 1 at a time. In HLS the compiler needs to somehow infer your registers and memories.

    That said, I think one of the problems the google team was struggling with is that in traditional HW development there is design and a separate verification team. The design team bought into Chisel since it would let them generate hardware more quickly, but the verification team just tried to apply their traditional verification methods on the _generated_ Verilog. This is almost like trying to test the assembly that a C++ compiler generates instead of trying to test the C++ program since all your testing infrastructure is setup for testing assembly code and that is "what we have always been doing".

    In order to catch verification up to modern Hardware Construction Languages [0] we need more powerful verification libraries that can allow us to build tests that can automatically adapt to the parameters that were supplied to the hardware generator. There are different groups working on this right now. The jury is still out on how to best solver the "verification gap". In case you are interested:

    - https://github.com/chiselverify/chiselverify

  • fault

    A Python package for testing hardware (part of the magma ecosystem) (by leonardt)

  • chiseltest

    The batteries-included testing and formal verification library for Chisel-based RTL designs.

  • amaranth

    A modern hardware definition language and toolchain based on Python

  • SpinalHDL

    Scala based HDL

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  • cocotb

    cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

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